This paper presents a highly efficient iterative Montgomery modular multiplication algorithm, wherein the computations of quotient and intermediate result in each iteration are done in parallel. This parallelism breaks the data dependency and thus reduces the computation latency. Moreover, this paper replaces required multiplications and additions in each iteration with compressions and encoding, thereby achieving a computation latency of order d+6 where d=⌈N/m⌉+2 is the number of iterations, N denotes the bitwidth of modulus M , and m is the number of bits of the multiplier that are processed in each iteration of the algorithm. Hardware realization of the proposed Montgomery modular multiplication on a Xilinx Virtex-7 FPGA device shows >41% computation latency saving and >31% area saving when N=1,024 and m=8 , compared with the best of previous state-of-art references. These savings amount to more than 63% reduction in terms of the area-latency product metric.
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An Iterative Montgomery Modular Multiplication Algorithm With Low Area-Time Product