This brief proposes an area-efficient AES design approach considering both application-specific integrated circuits (ASIC) and field-programmable gate arrays (FPGA) implementation characteristics. This brief focuses on optimizing and analyzing the design approach of Subbytes and MixColumns, which take up the most significant portion of AES hardware area. Furthermore, this brief presents an area-efficient AES intellectual property (IP) design by analyzing the trade-off relationship between area and clock cycles based on the datapath variations. The proposed AES IPs were designed using Verilog HDL and synthesized using Samsung 28nm standard cell library for performance comparison. The proposed AES IPs show the advanced normalized area efficiency of 70% over the existing AES design with the same datapath. Furthermore, the Xilinx UltraScale+ KCU116 evaluation board (XCKU5P) was used for FPGA verification and performance analysis. As a result, the FPGA implementation results show up to 36% better look-up table (LUT) utilization efficiency than the Xilinx AES IP, and up to 17.9 times better than the existing AES implementation results.
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Area-Efficient Intellectual Property (IP) Design of Advanced Encryption Standard