Fanout-Based Reliability Model for SER Estimation in Combinational Circuits
Fanout-Based Reliability Model for SER Estimation in Combinational Circuits
Abstract:
Soft errors in Integrated Circuits (ICs) have always been a major concern, particularly as CMOS technology nodes continue to shrink, resulting in higher frequency, lower power, and smaller areas, exacerbating radiation-induced soft errors. Therefore, Single Event Transient (SET) has become a crucial consideration in designing modern radiation-tolerant circuits, as it has the potential to cause failures in circuit outputs. This paper employs the concept of signal probability for transient fault propagation in circuits. Considering the issue of transient fault-masking, an error propagation model is presented for each fault-masking case. Furthermore, approaches are proposed for both probabilistic and time-based scenarios to address the impact of re-convergent paths on transient faults. Since considering re-convergent paths increases computational complexity, three computational approximations are proposed in this paper as a compromise to reduce the size of simulation runs as much as possible. We compared the simulation results with Monte-Carlo methods and HSPICE-based simulations to validate the proposed method. According to the comparison results on ISCAS-85 benchmarks, the proposed approach for estimating the SER exhibits an average accuracy of 95% while consuming less than 5% compared to traditional fault injection.
Index Terms:
Single event transient, single event rate, signal probability, logic circuit, logical masking, electrical masking, combinational circuits.
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Fanout-Based Reliability Model for SER Estimation in Combinational Circuits
