High-resolution sinusoidal pulsewidth modulation (SPWM) switching is beneficial in order to achieve compact size and fine sinusoidal output of dc-ac converters. In this article, a novel field-programmable gate array (FPGA) based high-definition SPWM (HD-SPWM) architecture is proposed for adopting a scheme of integrating a lower frequency PWM train to a high-frequency SPWM train in order to suppress inverter output harmonics while achieving high resolution output. An optimized FPGA-based two-stage finite-state-machine (FSM) architecture is designed, where the initial stage decides pulsewidths of a lower frequency PWM train based on the premeditated pulsewidth of the high-frequency SPWM train, whereas in the final stage, lower frequency PWM pulsewidths are integrated with the high-frequency SPWM pulsewidths to generate updated pulsewidths of high-frequency SPWM, i.e., HD-SPWM. Moreover, a preformulation mathematical model is established for the calculation of duty-cycle count values of pulse trains to support the online adjustment of modulation index (MI) of the HD-SPWM. The proposed generation has the benefits of harmonic mitigation, online fine adjustment of MI, low-processing time, and requirement of a minor segment of a medium-sized FPGA; thereby, providing a good tradeoff between larger designs and higher performance. Theoretical calculations, characteristics, and design contemplations are specified, and the HD-SPWM generation is demonstrated through experimentation with a Xilinx Spartan-3 FPGA board.
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FPGA-Based High-Definition SPWM Generation With Harmonic Mitigation Property for Voltage Source Inverter Applications