FPGA-Based Low-Bit and Lightweight Fast Light Field Depth Estimation
FPGA-Based Low-Bit and Lightweight Fast Light Field Depth Estimation
Abstract:
The 3-D vision computing is a key application in unmanned systems, satellites, and planetary rovers. Learning-based light field (LF) depth estimation is one of the major research directions in 3-D vision computing. However, conventional learning-based depth estimation methods involve a large number of parameters and floating-point operations, making it challenging to achieve low-power, fast, and high-precision LF depth estimation on a field-programmable gate-array (FPGA). Motivated by this issue, an FPGA-based low-bit, lightweight LF depth estimation network (L³FNet) is proposed. First, a hardware-friendly network is designed, which has small weight parameters, low computational load, and a simple network architecture with minor accuracy loss. Second, we apply efficient hardware unit design and software–hardware collaborative dataflow architecture to construct an FPGA-based fast, low-bit acceleration engine. Experimental results show that compared with the state-of-the-art works with total similar parameters (MSE), L³FNet can reduce the computational load by more than 109 times and cut parameters by approximately 8.7 times. Moreover, on the Xilinx official platform, it requires 96.5% lookup tables (LUTs), 80.67% digital signal processors (DSPs), 89.93% BlockRAM (BRAM), 85.82% LUT consumption, and 90.3% power consumption to achieve an efficient acceleration engine with a latency as low as 272 ms. The code and hardware design of the method are available at https://github.com/sansi-zhang/L3FNet.
Index Terms —
Depth estimation, field-programmable gate array (FPGA), light field (LF), lightweight, low-bit.
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