FPGA Implementation of a High Speed Efficient Single Precision Floating Point ALU
FPGA Implementation of a High Speed Efficient Single Precision Floating Point ALU
Abstract:
Modern-day computing processors require efficient floating point processing units that operate with high speed and low power consumption. Floating point computation operations are used in a wide variety of applications across different fields such as Engineering, AI, ML and DSP due to their inconceivable dynamic range and enhanced accuracy. These operations need to be performed quickly, with low power consumption and minimal hardware usage. In this paper, we present an efficient single precision floating point arithmetic logic unit with optimized architectures for addition and subtraction using carry look-ahead adder, multiplication using a modified booth encoder and division using the Goldschmidt algorithm. Our proposed architecture is designed using Verilog HDL and implemented on the Spartan 7 FPGA. The implemented design is compared with an existing ALU architecture and we demonstrate that the proposed ALU is 36% faster and more efficient in terms of power and area.
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FPGA Implementation of a High Speed Efficient Single Precision Floating Point ALU
