Low-Complexity Implementation of Real-Time Reconfigurable Low-Pass Equalizers
Low-Complexity Implementation of Real-Time Reconfigurable Low-Pass Equalizers
Abstract:
Implementation techniques and results for a recently proposed real-time reconfigurable low-pass equalizer (RLPE) consisting of a variable bandwidth (VBW) filter and a variable equalizer (VE) are presented. Both components utilize fixed finite-length impulse response (FIR) filters combined with a few general multipliers, resulting in lower area and power consumption compared to a general FIR filter, despite requiring more multiplications. This is because the constant multipliers in the fixed FIR filters of the RLPE can be optimized for implementation. An additional advantage is that the proposed RLPE does not require online design. Various implementation alternatives for fixed FIR filters, including ways to increase the frequency, are evaluated to optimize the implementation of the RLPE. Several versions of the proposed RLPE and a general FIR filter for comparison are implemented using a 28-nm fully depleted silicon on insulator (FD-SOI) standard cell library. The results demonstrate that the RLPE scalable design requires less power and area than the general equalizer, and although the frequency of the baseline implementation is lower, the design can reach the same frequency while still having significantly less power and area. The proposed approach breaks the area break barrier in the polynomial order by allowing the use of fewer constant registers compared to general FIR filters. Instead, this method reuses coefficient multipliers in the problem to produce correct results. The area of the proposed construction is reduced between 49% and 63% for different frequencies, with an area decrease in the range of 64%–67%, by the proposed RLPE compared to a general FIR filter.
