Digital true-random number generators (TRNG) are increasingly employed to generate random channels in low-power resource-constrained IoT devices at the network edge. However, their susceptibility to process variations, or even intrusion attacks, degrade the generated entropy requiring an on-the-fly processor for detection of bias variations and correction. This work proposes a two-step search process to implement an optimized search that minimizes the latency (number of clock-cycles) for bias correction implemented on a FPGA platform. The first step implements a subset of NIST tests for entropy validation and an additional auto correlator is used for entropy validation and bias detection on-the-fly in the second step. Measured results with the proposed algorithm implemented on FPGA shows significant improvement in the probability of bias correction with low number of trials. The measured power consumption of the TRNG and the bias correction is 10.22mW and 10.96mW respectively at 1.25 V with 18 kHz throughput for three random channels.
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Low-Latency Reconfigurable Entropy Digital True Random Number Generator With Bias Detection and Correction