In this paper, novel circuits for XOR/XNOR and simultaneous XOR–XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation. We also propose six new hybrid 1-bit full-adder (FA) circuits based on the novel full-swing XOR–XNOR or XOR/XNOR gates. Each of the proposed circuits has its own merits in terms of speed, power consumption, power delay product (PDP), driving ability, and so on. To investigate the performance of the proposed designs, extensive HSPICE and Cadence Virtuoso simulations are performed. The simulation results, based on the 65-nm CMOS process technology model, indicate that the proposed designs have superior speed and power against other FA designs. A new transistor sizing method is presented to optimize the PDP of the circuits. In the proposed method, the numerical computation particle swarm optimization algorithm is used to achieve the desired value for optimum PDP with fewer iterations. The proposed circuits are investigated in terms of variations of the supply and threshold voltages, output capacitance, input noise immunity, and the size of transistors.Software implementation:
TODAY, ubiquitous electronic systems are an inseparable part of everyday life. Digital circuits, e.g., microprocessors, digital communication devices, and digital signal processors, comprise a large part of electronic systems. As the scale of integration increases, the usability of circuits is restricted by the augmenting amounts of power and area consumption. Therefore, with the growing popularity and demand for the battery-operated portable devices such as mobile phones, tablets, and laptops, the designers try to reduce power consumption and area of such systems while preserving their speed. Optimizing the W/L ratio of transistors is one approach to decrease the power-delay product (PDP) of the circuit while preventing the problems resulted from reducing the supply voltage. The efficiency of many digital applications appertains to the performance of the arithmetic circuits, such as adders, multipliers, and dividers. Due to the fundamental role of addition in all the arithmetic operations, many efforts have been made to explore efficient adder structures, e.g., carry select, carry skip, conditional sum, and carry look-ahead adders. Full adder (FA) as the fundamental block of these structures is at the center of attention. Based on the output voltage level, FA circuits can be divided into full-swing and non full-swing categories. Standard CMOS, complementary pass-transistor logic (CPL), transmission gate (TG), transmission function, 14T (14 transistors) 16T, and hybrid pass logic with static CMOS output drive full adder (HPSC), FAs are the most important full-swing families. Non full-swing category comprises of 10T, 9T, and 8T. In this paper, we evaluate several circuits for the XOR or XNOR (XOR/XNOR) and simultaneous XOR and XNOR (XOR–XNOR) gates and offer new circuits for each of them. Also, we try to remove the problems existing in the investigated circuits. Afterward, with these new XOR/XNOR and XOR–XNOR circuits, we propose six new FA structures.Disadvantages:
Proposed XOR–XNOR Circuit
The non full-swing XOR/XNOR circuit is efficient in terms of the power and delay. Furthermore, this structure has an output voltage drop problem for only one input logical value. To solve this problem and provide an optimum structure for the XOR/XNOR gate is proposed. For all possible input combinations, the output of this structure is full swing. The proposed XOR/XNOR gate does not have NOT gates on the critical path of the circuit.
The input A and B capacitances of the XOR circuit shown in are not symmetric, because one of these two should be connected to the input of NOT gates and another should be connected to the diffusion of NMOS transistor. Furthermore, the input capacitances of transistors N2 and N3 are not equal in the optimal situation (minimum PDP). The Full-swing XOR/XNOR and XOR–XNOR circuits Also, the order of input connections to transistors N2 and N3 will not affect the function of the circuit. Thus, it is better to connect the input A, which is also connected to the NOT gates, to the transistor with smaller input capacitance. By doing this, the input capacitances are more symmetrical, and thus, the delay and power consumption of the circuit will be reduced. To clarify which transistor (N2 or N3) has larger input capacitance, let us consider the condition that the inputs change from AB = 00 to AB = 10. In this condition, as the RC model of XOR is shown before, the transistor N2 is driving only the capacitance of node X from GND to V DD – V thn , so it will not require lower RN2. But, when the inputs change from AB = 10 to AB = 11.
where W min is the minimum transistor width, R min is the ON-state resistance for the NMOS transistor with W min, C dmin is the diffusion capacitance of the transistor, and a is the total size of the transistors P2, P3, and N4.
where Cgmin is the gate capacitance of the transistor, and C total is all capacitances that are switched. By assuming Cdmin ˜ Cgmin= C and a = 3.
Finally, by having the value of delay and power dissipation, the PDP of the circuit can be obtained. For a better comparison, the normalized PDP (PDPn) is considered.
The value of normalized PDP with a = 3 for 1 = k N2 , k N3 = 4.It also shows that, in the optimal condition, the value of kN3 is bigger than that of kN2. Therefore, the W/L ratio of the transistor N3 is larger than that of the transistor N2. Thus, the input capacitance of transistor N3 is higher than that of transistor N2 and, to obtain the optimal circuit, it is better to connect input A to the transistor N2. The advantages of the proposed XOR/XNOR circuits are full-swing output, good driving capability, smaller number of interconnecting wires, and straightforward circuit layout.The circuit layout of the proposed XOR and XNOR gates, respectively, designed for minimum power consumption.
Proposed XOR–XNOR Circuit
The delay of XOR and XNOR outputs of this circuit is almost identical, which reduces the glitch in the next stage. Other advantages of this circuit are good driving capability, full-swing output, as well as robustness against transistor sizing and supply voltage scaling. The proposed XOR/XNOR and simultaneous XOR–XNOR structures were compared with all the above-mentioned structures. The simulation results at TSMC 65-nm technology and 1.2-V power supply voltage (VDD) are shown in Table I. The input pattern is used as all possible input combinations have been included.
The maximum frequency for the inputs was 1 GHz and 4× unit-size inverter (FO4) was connected to the output (as a load). The size of transistors has been selected for optimum PDP by using the proposed transistor sizing method, which the proposed procedure will be described. The optimum size of transistors for each XOR/XNOR and XOR–XNOR circuits are expressed in Table I. In the output rise and fall transition, the delay is calculated from 50% of the input voltage level to 50% of the output voltage level. The PDP will be calculated by multiplying the worst case delay by the average power consumption of the main circuit. The results indicate that the performance of the proposed XOR/XNOR and simultaneous XOR–XNOR structures is better as mentioned earlier and according to the obtained results, the XOR circuit has a better performance than its XNOR circuit. The proposed circuit for simultaneous XOR–XNOR has better efficiency in all three calculated parameters (delay, power dissipation, and PDP) when it is compared with other XOR–XNOR gates. The proposed XOR–XNOR circuit is saving almost 16.2%–85.8% in PDP, and it is 9%–83.2% faster than the other circuits. The circuits of above mentioned have the very high delay due to its output feedback (which have the slow response problem). As can be seen in Table I, the efficiency is much worse and its delay is four times more than that of other circuits. Table I indicates that the structures have shown a better performance, which have the minimum NOT gates on the critical path and also have not feedback on the outputs to correct the output voltage level. To better evaluate the XOR–XNOR circuits, they are simulated at different power supply voltages from 0.6 to 1.5 V and also at different output loads from FO1 to FO16. The results of these two simulations are shown. The proposed XOR–XNOR circuit has the best performance in both simulations when compared with other structures. Proposed FAs.
We proposed six new FA circuits for various applications which have been shown. Also, the circuit layout of proposed FA cell is shown. These new FAs have been employed swith hybrid logic style, and all of them are designed by using the proposed XOR/XNOR or XOR–XNOR circuit. The well-known four-transistor 2-1-MUX structure is used to implement the proposed hybrid FA cells. This 2-1-MUX is created with TG logic style that has no static and short-circuit power dissipation.It shows the circuit of first proposed hybrid FA (HFA-20T) which is made by two 2-to-1 MUX gates and the XOR–XNOR gate. The circuit of HFA-20T has not high power consumption NOT gates on critical path and consists of 20 transistors. The advantages of this structure are full-swing output, low power dissipation and very high speed, robustness against supply voltage scaling, and transistor sizing. If B = 1, then the output Cout signal equals to the input signal A or B. But to equalize the inputs capacitance, both of the input signals A and B are used for implementation and are connected to the transistors N9 and P10, respectively. The only problem of HFA-20T is reduction of the output driving capability when it is used in the chain structure applications, such as ripple carry adder. Of course, this problem exists in the circuits that use the transmission function theory in their implementation without buffering output.Advantages: