Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery for Reliable Applications
Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery for Reliable Applications
Abstract:
Transistor sizing and spacing are constantly decreasing due to the continuous advancement of CMOS technology. The charge of the sensitive nodes in the static random access memory (SRAM) cell gradually decreases, making the SRAM cell more and more sensitive to soft errors, such as single-node upsets (SNUs) and double-node upsets (DNUs). Therefore, two types of radiation-hardened SRAM cells are proposed in this article. First, a low-power DNU self-recovery S6P8N cell is proposed. This cell can realize SNU self-recovery from all sensitive nodes as well as realize partial DNU self-recovery and has low-power consumption overhead. Second, we propose a high-speed DNU self-recovery S8P6N cell, which has a soft-error tolerance equivalent to the S6P8N. Furthermore, it reduces the read access time (RAT) and write access time (WAT). Simulation results show that the proposed cells are self-recovery for all SNUs and most of DNUs. Compared with RHBD12, QC8M2T, QC8CE12T, RHM10T, SEA14T, RHM-12T, S8P4R, S8P8M, RH-14T, HRLP16T, GC16T, and HRH-12T, the average power consumption of S6P8N is reduced by 48.78%, and the average power consumption of S8P6N is reduced by 26.34%. At the same time, WAT and RAT are reduced by 9.07% and 36.84%, respectively.
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Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery for Reliable Applications
