Optimized Algorithms for FPGA Implementation of PDCCH Chain for 5G-NR Base Station
Optimized Algorithms for FPGA Implementation of PDCCH Chain for 5G-NR Base Station
Abstract:
The physical layer in a cellular network base station typically runs on a field programmable gate array (FPGA) to enable reconfigurability and adaptability to meet future demands of the network with sufficient computational power. This work proposes a novel architecture and algorithms for the FPGA implementation of the fifth-generation (5G) new radio (NR) physical downlink control channel (PDCCH) using the 3GPP procedures for downlink control information (DCI) processing, including sub-block interleaver, bit selection, scrambling, golden sequence generation, and modulation. The proposed algorithms are optimized to meet 5G-NR frame timings for DCI processing, while minimizing power consumption and hardware resource utilization. We perform rigorous testing including all corner cases to benchmark our designs in i) standalone mode, and ii) integrated form for the end-to-end PDCCH processing. The PDCCH implementation, with maximum DCI payload, using the proposed architecture and algorithms achieves 1.5μs latency, 1.9% hardware resource utilization, and throughput greater than 10 Gbps/W power efficiency. With a subcarrier spacing Δf = 30 kHz, it can multiplex DCI to schedule up to 20 and 40 users for orthogonal frequency division multiplexing (OFDM) and two OFDM symbols long PDCCH respectively.
