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IEEE Transactions on VLSI 2025

Following Novelty based Research Projects not yet Published in Any Journal 

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Hardware Efficient Approximate
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Design of a Hardware Efficient Approximate 4-2 Compressor for Multiplication in Image Processing

Original price was: ₹16,000.00.Current price is: ₹8,000.00.
Source : Verilog HDL

Base Paper Abstract:

This letter presents a novel hardware-efficient approximate 4-2 compressor design that significantly enhances accuracy through a systematic analysis of input patterns obtained from practical applications. We incorporate a majority operation and a compound gate in the compressor design to effectively boost hardware efficiency in multiplications. Our design approach results in substantial error reductions, with normalized mean error distance (NMED) and mean relative error distance (MRED) decreasing by up to 74.84% and 82.04%, respectively, compared to existing approximate multipliers discussed in this letter. When implemented in a 32-nm CMOS technology, the approximate multiplier adopting the proposed 4-2 compressor achieves excellent hardware efficiency, reducing area, power, and energy consumption by up to 8.95%, 13.02%, and 13.02%, respectively, compared to the other alternatives. Moreover, our design delivers enhanced performance in image processing tasks, achieving up to a 4.84× increase in peak signal-to-noise ratio (PSNR) compared to other designs, all while optimizing hardware efficiency. Index Terms—Approximate multiplier, majority operation, compound gate, image processing, approximate 4-2 compressor.

List of the following  materials will be included with the Downloaded Backup:
1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Existing and Proposed Project Comparison with output video 
3. Basic Documentation (20 to 30 Pages):
3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
4. Online Support ( Any Desk / Zoom / Google Meet)
 
sale OFFER 50%
10T-SRAM Cell for AES Systems
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Full-Array Boolean Logic CIM Macro with Self-Recycling 10T-SRAM Cell for AES Systems

Original price was: ₹12,000.00.Current price is: ₹6,000.00.
Source : Tanner EDA

Base Paper Abstract:

Computing in memory (CIM), which alleviates the need to transfer a large amount of data between processor and memory, significantly reducing latency and energy consumption, is a promising new computing architecture for addressing the von Neumann bottleneck problem. This article proposes a CIM array structure composed of self-recycling 10T static random access memory (SRAM) cells, which can realize orthogonal data writing, and multiple Boolean logical operations for the entire array. The self-recycling and full-array activation characteristics are extremely suitable for accelerating diverse data processing algorithms such as the Advanced Encryption Standard (AES). A 4-kb SRAM is implemented in 55-nm CMOS technology to verify the effectiveness of the design. Compared with other state-of-threat architectures, the throughput and the operating frequency of the proposed CIM macro are increased to 843 GOPS/kb (2.64×) and 823.7 MHz (2.6×), respectively. The energy efficiency reaches 246.9 TOPS/W. When applied to the AES, the energy consumption is 35.77% less than the digital CIM architecture that is not self-recycling.

List of the following  materials will be included with the Downloaded Backup:
1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Existing and Proposed Project Comparison with output video 
3. Basic Documentation (20 to 30 Pages):
3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
4. Online Support ( Any Desk / Zoom / Google Meet)
 
sale OFFER 36%
Odor Identification
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FPGA Implementation for Odor Identification with Depthwise Separable Convolutional Neural Network

Original price was: ₹55,000.00.Current price is: ₹35,000.00.
Source : Verilog HDL

Base Paper Abstract:

The integrated electronic nose (e-nose) design, which integrates sensor arrays and recognition algorithms, has been widely used in different fields. However, the current integrated e-nose system usually suffers from the problem of low accuracy with simple algorithm structure and slow speed with complex algorithm structure. In this article, we propose a method for implementing a deep neural network for odor identification in a small-scale Field-Programmable Gate Array (FPGA). First, a lightweight odor identification with depthwise separable convolutional neural network (OIDSCNN) is proposed to reduce parameters and accelerate hardware implementation performance. Next, the OI-DSCNN is implemented in a Zynq-7020 SoC chip based on the quantization method, namely, the saturation-flooring KL divergence scheme (SF-KL). The OI-DSCNN was conducted on the Chinese herbal medicine dataset, and simulation experiments and hardware implementation validate its effectiveness. These findings shed light on quick and accurate odor identification in the FPGA.

List of the following  materials will be included with the Downloaded Backup:
1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Existing and Proposed Project Comparison with output video 
3. Basic Documentation (20 to 30 Pages):
3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
4. Online Support ( Any Desk / Zoom / Google Meet)
 
sale OFFER 33%
CNN_Analog_Kernel_Multiplication
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Design of a Low-Power Analog Integrated Deep Convolutional Neural Network

Original price was: ₹12,000.00.Current price is: ₹8,000.00.
Source : Verilog HDL

Base Paper Abstract:

In this article, a framework for the analog implementation of a deep convolutional neural network (CNN) is introduced and used to derive a new circuit architecture which is composed of an improved analog multiplier and circuit blocks implementing the ReLU activation function and the argmax operator. The operating principles of the individual blocks, as well as those of the complete architecture, are analysed and used to realize a low-power analog classifier, consuming less than 1.8 µW. The proper operation of the classifier is verified via a comparison with a software equivalent implementation and its performance is evaluated against existing circuit architectures. The proposed architecture is implemented in a TSMC 90-nm CMOS process and simulated using Cadence IC Suite for both schematic and layout design. Corner and Monte Carlo mismatch simulations of the schematic and the physical circuit (post layout) were conducted to evaluate the effect of transistor mismatches and process voltage temperature (PVT) variations and to showcase a proposed systematic method for offsetting their effect.

List of the following  materials will be included with the Downloaded Backup:
1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Existing and Proposed Project Comparison with output video 
3. Basic Documentation (20 to 30 Pages):
3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
4. Online Support ( Any Desk / Zoom / Google Meet)
 
sale OFFER 50%
TSPC Dual-Edge Triggered Flip-Flops
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Low-Power, Low-Energy, Static, Contention-Free, TSPC Dual-Edge Triggered Flip-Flops

Original price was: ₹12,000.00.Current price is: ₹6,000.00.
Source : Tanner EDA

Base Paper Abstract:

The dual edge-triggered flip-flop samples the data on both the positive and negative edges of the clock. Hence, it can lead to lower clock relative power consumption as compared to the single-edge triggered flip-flop while maintaining the same data throughput. In this paper, we present two low-power, low-energy dual-edge triggered TSPC flip-flops based on latch-mux type methodology. These two flip-flops, Low-Power at Low Data Activity (LPLD-DET), and Low-Power at High Data Activity (LPHD-DET) are suitable for low-power application. These flip-flops are fully static and contention-free. The post-layout simulation results in TSMC CMOS 65 nm technology suggest that the proposed LPLD-DET is the most power-efficient dual-edge triggered flip-flop for low data activities up to 30%, and LPHD-DET is the most power-efficient dual-edge triggered flip-flop for higher data activities from 45% compared to the other state of-the-art dual-edge triggered TSPC flip-flops.

List of the following  materials will be included with the Downloaded Backup:
1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Existing and Proposed Project Comparison with output video 
3. Basic Documentation (20 to 30 Pages):
3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
4. Online Support ( Any Desk / Zoom / Google Meet)
 
sale OFFER 36%
FP16 Multi-Operand Operations
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A Pipelined Fused Multiply-Add Architecture for Configurable FP16 Multi-Operand Operations

Original price was: ₹25,000.00.Current price is: ₹16,000.00.
Source : Verilog HDL

Base Paper Abstract:

Multiple precision modes are needed for a floating-point processing element (PE) because they provide flexibility in handling different types of numerical data with varying levels of precision and performance metrics. Performing high-precision floating-point operations has the benefits of producing highly precise and accurate results while allowing for a greater range of numerical representation. Conversely, low-precision operations offer faster computation speeds and lower power consumption. In this paper, we propose a configurable multi-precision processing element (PE) which supports Half Precision, Single Precision, Double Precision, BrainFloat-16 (BF-16) and TensorFloat-32 (TF-32). The design is realized using GPDK 45 nm technology and operated at 281.9 MHz clock frequency. The design was also implemented on Xilinx ZCU104 FPGA evaluation board. Compared with previous state-of-the-art (SOTA) multiprecision PEs, the proposed design supports two more floating point data formats namely BF-16 and TF-32. It achieves the best energy performance with 2368.91 GFLOPS/W and offers 63% improvement in operating

List of the following  materials will be included with the Downloaded Backup:
1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Existing and Proposed Project Comparison with output video 
3. Basic Documentation (20 to 30 Pages):
3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
4. Online Support ( Any Desk / Zoom / Google Meet)
 
sale OFFER 36%
Brain Tumor Detection
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FPGA-Based Brain Tumor Detection from MRI Using 3×3 Convolution Soft IP Core with Stride 1

Original price was: ₹25,000.00.Current price is: ₹16,000.00.
Source : Verilog HDL

Base Paper Abstract:

This paper presents an efficient FPGA-based system for automatic brain tumor detection from MRI images using a 3x3 convolutional edge detection method with stride 1. The proposed architecture is developed as a soft IP core in Verilog HDL and synthesized on a Xilinx Zynq 7000 FPGA platform. The system applies a customized 3x3 convolution kernel over each MRI image with stride 1, ensuring that every pixel is processed and fine image details are preserved for accurate tumor detection. Edge detection results are used to segment and highlight abnormal regions, and a thresholding mechanism is employed to differentiate between normal and abnormal images. Hardware resource utilization—including look-up tables (LUTs), flip-flops (FFs), and power consumption—is analyzed after synthesis to verify system efficiency. Experimental results confirm that the proposed FPGA implementation provides real-time processing and reliable brain tumor detection with low power usage, making it suitable for portable and embedded medical devices. The stride 1 approach guarantees maximum detection accuracy and detailed edge representation in all test cases.

List of the following  materials will be included with the Downloaded Backup:
1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Existing and Proposed Project Comparison with output video 
3. Basic Documentation (20 to 30 Pages):
3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
4. Online Support ( Any Desk / Zoom / Google Meet)
 
sale OFFER 45%
Winograd Convolution
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Hardware Implementation of Improved Banker’s Fixed-Point Rounding Algorithm

Original price was: ₹55,000.00.Current price is: ₹30,000.00.
Source : Verilog HDL

Base Paper Abstract:

In recent years, FPGA-based convolutional neural networks (CNNs) accelerator has received tremendous research interest, especially in fields such as autonomous driving and robotics. For the purpose of accelerating convolution computations, Winograd fast convolution algorithm is frequently employed. However, during implementation of the Winograd algorithm on FPGA, multiple rounding operations occur, and the accuracy of these operations substantially impacts the convolution results. The banker’s rounding algorithm, compared to other rounding algorithms, has advantages such as a more symmetric error distribution and smaller errors, making it suitable for Winograd convolution computation. However, the conventional banker’s rounding algorithm is proposed for floating-point calculations, yet FPGA implements fixed-point arithmetic. Moreover, it frequently rounds 0.5 to 0, leading to the issue of convolution weight invalidation and introducing significant errors. To overcome these challenges, an improved hardware circuit designed for implementing the fixed-point banker’s rounding algorithm is proposed. Experimental results show that compared with common rounding up and rounding down methods, the proposed algorithm exhibits smaller errors and effectively resolves the issue of weight invalidation in conventional banker’s rounding, leading to a significant 55.6% improvement in computational accuracy.

List of the following  materials will be included with the Downloaded Backup:
1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Existing and Proposed Project Comparison with output video 
3. Basic Documentation (20 to 30 Pages):
3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
4. Online Support ( Any Desk / Zoom / Google Meet)
 
sale OFFER 38%
Lightweight, High-Entropy TRNG
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Lightweight, High-Entropy TRNG Using Quad Cross-Coupled Feedback Architecture

Original price was: ₹16,000.00.Current price is: ₹10,000.00.
Source : Verilog HDL

Base Paper Abstract:

This paper presents a lightweight, high-entropy true random number generator architecture featuring an innovative quad cross-coupled feedback mechanism to enhance randomness. The primary goal is to develop an efficient and secure true random number generator that addresses the growing demand for reliable random number generation in cryptographic and security-critical applications. The motivation stems from the need to improve entropy, reduce resource utilization, and ensure robustness across varying technologies. With the intention of achieving near-perfect randomness, the Quad-Input Oscillating Circuit module integrates self-coupled, jitter-inducing ring oscillators with cross-coupled feedback loops to induce metastability. Comprehensive evaluations confirm a Shannon entropy of 0.999818, a minimum entropy of 0.977257, and a collision entropy of 0.999636. The design was synthesized using Synopsys Design Compiler at 45 nm, 32 nm, and 14 nm, achieving a maximum frequency of 6.7 GHz, power consumption as low as 72 μW, and area utilization of 24 μm2 at 14 nm. Rigorous validation through multiple statistical test suites, including the AIS-31, Autocorrelation, Deviation, Diehard, the National Institute of Standards and Technologies SP800- 22 and SP800-90B, and TestU01, confirms its efficiency and reliability. Real random bits were implemented as oscilloscope viewable signals on the Cyclone V Field Programmable Gate Array developed by Altera, representing a significant advancement in secure random number generation technologies.

List of the following  materials will be included with the Downloaded Backup:
1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Existing and Proposed Project Comparison with output video 
3. Basic Documentation (20 to 30 Pages):
3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
4. Online Support ( Any Desk / Zoom / Google Meet)
 
sale OFFER 38%
Galois LFSR with dynamic feedback path
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A Design of lightweight true random number generator based on Galois LFSR with dynamic feedback path

Original price was: ₹16,000.00.Current price is: ₹10,000.00.
Source : Verilog HDL

Base Paper Abstract:

The Linear Feedback Shift Register (LFSR) is a widely utilized circuit structure in electronic systems, often employed as a Pseudo Random Number Generator (PRNG) for generating pseudo random sequence. However, in light of the significant challenges associated with privacy protection and data encryption, traditional PRNGs have frequently failed to meet the increasing security demands of electronic systems. In contrast, True Random Number Generators (TRNGs), have emerged as essential security primitives within the realm of hardware security, garnering increasing attention. In response to these challenges, this paper proposes a novel lightweight TRNG architecture based on Galois LFSR. This innovation design incorporates inverters and two-to-one multiplexers to modify the feedback path. The proposed structure has been implemented on AMD Xilinx Artix-7 and Kintex-7 FPGA boards. Notably, it demonstrates a resource-efficient design, utilizing only 17 Look-Up Tables (LUTs) and 9 D Flip-Flops (DFFs), while achieving random number with throughput of 300Mbps. Furthermore, the structure successfully passes both randomness test and robustness test, indicating its promising application potential in secure electronic systems.

List of the following  materials will be included with the Downloaded Backup:
1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Existing and Proposed Project Comparison with output video 
3. Basic Documentation (20 to 30 Pages):
3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
4. Online Support ( Any Desk / Zoom / Google Meet)
 
sale OFFER 38%
Approximate Multipliers
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Design and Analysis of Energy Efficient Approximate Multipliers for Image Processing and DNN

Original price was: ₹16,000.00.Current price is: ₹10,000.00.
Source : Verilog HDL

Base Paper Abstract:

Numerous obstacles in enhancing the performance of computing systems have spurred the emergence of approximate computing. Extensive studies have been reported on approximate computing to develop high-performance, energy-efficient hardware designs tailored to error-resilient applications. In this brief, we proposed 8-bit approximate multipliers with 15 levels of accuracy using three techniques: recursive, bit-wise, and hybrid approximation using partial bit OR (PBO). Compared to the existing multipliers, investigated designs have significantly improved the area, power, delay, Power Delay Product (PDP), and Power Area Delay Product (PADP) by 41.68%, 73.16%, 35.57%, 72.65%, and 75.42% respectively on average. On resemblance with the accurate multiplier, the area, power, delay, PDP, and PADP were enhanced by 54.41%, 57.57%, 25.73%, 60.14%, and 74.33% correspondingly on average. Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM) values surpassing (30 dB, 94%), (31 dB, 96%), and (26 dB, 95%) by applying them to benchmarks in image smoothing, edge detection, and image sharpening successively. Moreover, upon scrutinizing the efficacy of multipliers in hardware implementations of deep neural networks attaining the performance exceeding 95%. The obtained results confirm that suggested multipliers are well-suited for their widespread applications.

List of the following  materials will be included with the Downloaded Backup:
1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Existing and Proposed Project Comparison with output video 
3. Basic Documentation (20 to 30 Pages):
3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
4. Online Support ( Any Desk / Zoom / Google Meet)
 
IEEE Transactions on VLSI 2025, VLSI 2025 IEEE Project, VLSI Low Power 2025 Project, VLSI High Speed 2025 Project, VLSI Area Efficient 2025 Project, Low Cost VLSI 2025 Projects, High Speed VLSI Design 2025 projects ( CDMA, RTOS, DSP, RF, IF, etc), Low Power VLSI Design 2025 projects, Area Efficient VLSI Design 2025 projects , Audio processing VLSI Design 2025 projects, Signal Processing VLSI Design 2025 projects, Image Processing VLSI Design 2025 projects, Backend VLSI Design 2025 projects ( CMOS, TFET, BisFET, FeFET, etc), Timing & Delay Reduction VLSI 2025 Projects, Internet of Things VLSI 2025 Projects, Testing, Reliability and Fault Tolerance VLSI Projects, VLSI Applications ( Communicational, Video, Security, Sensor Networks, etc), SOC VLSI Projects, Network on Chip VLSI Projects, Wireless Communication VLSI Projects, VLSI Verifications Projects ( UVM, OVM, VVM, System Verilog).

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