₹10,000.00Original price was: ₹10,000.00.₹7,000.00Current price is: ₹7,000.00.
Source : VHDL
Abstract:
The need of low area and high speed Multiplier is increasing as the need of high speed processors are needed. The multipliers used in Square and cube architecture have to be more efficient in area and also in speed. In this paper a multiplier is implemented based on Nikhilam sutra with binary excess unit. The ripple carry adder in the multiplier architecture increases the speed of addition of partial products. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.
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₹25,000.00Original price was: ₹25,000.00.₹16,000.00Current price is: ₹16,000.00.
Source : VHDL
Abstract:
Watermarking the digital data is a familiar technique to authenticate and resolve the copyright issues of multimedia data. This paper proposes a new VLSI architecture for watermarking grayscale images using weighted median prediction operation, as this mechanism will have a minimum computation complexity. In this VLSI based data hiding process the secret digital signature is hidden in the host image and analyzed with the PSNR value and Payload capacity.
List of the following materials will be included with the Downloaded Backup:
₹20,000.00Original price was: ₹20,000.00.₹14,000.00Current price is: ₹14,000.00.
Source : VHDL
Abstract:
The watermarking is the important multimedia content for authentication and security in nowadays. We are proposed to implement the watermarking in FPGA with VLSI architecture. And also use the Haar discrete wallet transform and bit plane slicing for creating the water marking images and extracted watermark images. The area, power, delay of the proposed architecture is analysis using Xilinx 14.2.
List of the following materials will be included with the Downloaded Backup:
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