Objective:
- To design and implement 6T, 8T, and 9T SRAM cells using 45 nm CMOS technology.
- To develop and simulate 8×8 SRAM array architectures for all three SRAM designs.
- To analyse the performance of SRAM cells under normal binary input conditions.
- To evaluate SRAM performance using ECG-oriented digital stimuli derived from the MIT-BIH dataset.
- To compare power consumption, delay, and area among 6T, 8T, and 9T SRAM architectures.
- To study the impact of ECG-based digital data patterns on SRAM read and write operations.
- To verify stable data storage and retrieval of digitized ECG samples in SRAM memory.
- To identify the advantages and trade-offs of 9T SRAM compared to conventional SRAM designs.
- To validate SRAM functionality and performance using Tanner EDA simulation tools.
- To demonstrate the suitability of the proposed 9T SRAM for ECG-oriented digital signal storage applications.
Proposed abstract:
Static Random Access Memory (SRAM) plays a vital role in modern digital and embedded systems due to its high speed, simple structure, and compatibility with CMOS technology, and it is widely used in processors, biomedical devices, and real-time signal storage applications such as ECG monitoring systems. While conventional 6T SRAM offers compact area and low complexity, it suffers from read stability and delay issues at scaled technologies, whereas 8T and 9T SRAM architectures improve read reliability and performance at the cost of increased area and transistor count. In biomedical applications like ECG signal storage, where reliable and low-power digital data handling is required, selecting an optimal SRAM architecture becomes challenging. Most existing works focus either on conventional SRAM performance using generic binary inputs or on advanced compute-in-memory designs, with limited analysis on ECG-oriented digital data patterns. In this work, a comparative design and analysis of 6T, 8T, and 9T SRAM cells and their corresponding 8×8 array architectures is presented for ECG-oriented digital signal storage. Digitized ECG samples from the MIT-BIH arrhythmia database are used as realistic biomedical input stimuli, ensuring practical relevance while maintaining purely digital storage. All SRAM architectures are designed and simulated in 45 nm CMOS technology using Tanner EDA. The proposed 9T SRAM demonstrates improved delay performance and reduced power consumption compared to 6T and 8T designs, with a moderate area overhead. Performance evaluation is carried out at both single-cell and array levels under normal binary inputs and ECG-based digital stimuli, validating stable operation and consistent behaviour. The novelty of this work lies in the systematic comparison of multiple SRAM architectures under ECG-oriented digital workloads, providing design insights for low-power and reliable biomedical memory applications.
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Comparative Design of 6T, 8T, and 9T SRAM Cells and 8×8 Arrays for ECG-Oriented Digital Signal Storage
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