A compact and energy-efficient level shifter is essential in voltage-scaled systems such as low-power processors, sensor nodes, and memory-centric architectures where wide voltage interfacing and fast signal translation are required. Existing level shifters provide good conversion range and moderate delay, but they often suffer from large transistor counts, increased area, higher leakage, and reduced efficiency when operated in deeply scaled technologies. These limitations become more significant in memory-dominated systems, where level shifting directly affects the stability and read performance of SRAM cells. This paper level shifter-based and buffer-assisted structures use 7 to 13 transistors and introduce additional parasitic loading that limits speed and increases dynamic power. To address these issues, this work proposes an optimized and ultra-compact level shifter using only 5 transistors in 45-nm CMOS technology. The design restructures the current mirror and feedback path to reduce short-circuit current, minimize leakage, and preserve a voltage gain of about 6.02 dB while cutting device count by more than half compared to earlier designs. A key novelty of this work is the integration of the proposed level shifter into a 6T SRAM read-assist path, where the amplified output enhances bit line differential swing, improves read stability, and reduces latency without adding substantial area or energy overhead. The proposed circuit is evaluated through schematic-level simulations using Tanner EDA, measuring delay, power, minimum operating voltage, gain, and stability under typical and corner conditions. Results confirm that the five-transistor architecture achieves lower power consumption, reduced delay, and smaller silicon area while improving memory read performance, demonstrating its suitability for compact and energy-constrained system-on-chip applications.

Software Implementation:

• Tanner EDA

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Ultra-Low-Voltage Level Shifter with Optimized Switching for SRAM Readout Enhancement in 45 nm CMOS