Objective:

• To minimize overall power consumption and silicon area by adopting a largely digital, open-loop clock generation architecture that avoids additional PLLs or complex analog calibration circuits.
• To design and implement a fractional output divider (FOD) architecture in 45-nm CMOS and 65nm technology using Tanner EDA, capable of generating multiple fractional clock frequencies from a single high-frequency reference clock.
• To ensure reliable operation at a reduced supply voltage, targeting ultra-low-power system-on-chip (SoC) applications while maintaining functional robustness across process variations.
• To implement and validate DTC gain, offset, and foreground INL calibration techniques under low-voltage conditions using Tanner-based design and simulation.
• To achieve acceptable clock quality in terms of jitter performance suitable for system-on-chip applications.