Objective:
- To minimize overall power consumption and silicon area by adopting a largely digital, open-loop clock generation architecture that avoids additional PLLs or complex analog calibration circuits.
- To design and implement a fractional output divider (FOD) architecture in 45-nm CMOS and 65nm technology using Tanner EDA, capable of generating multiple fractional clock frequencies from a single high-frequency reference clock.
- To ensure reliable operation at a reduced supply voltage, targeting ultra-low-power system-on-chip (SoC) applications while maintaining functional robustness across process variations.
- To implement and validate DTC gain, offset, and foreground INL calibration techniques under low-voltage conditions using Tanner-based design and simulation.
- To achieve acceptable clock quality in terms of jitter performance suitable for system-on-chip applications.
Proposed abstract:
Fractional output dividers are widely used in system-on-chip applications such as processors, communication systems, data converters, and low-power embedded devices for generating multiple clock frequencies from a single reference source. Compared to conventional multi-PLL clocking systems, fractional output divider based architectures offer advantages such as reduced silicon area, lower power consumption, fast frequency switching, and simpler integration. However, these architectures also suffer from challenges including timing jitter, fractional spurs, and sensitivity to digital-to-time converter nonlinearity, especially when operating at low supply voltages. With the increasing demand for ultra-low-power SoCs, reliable clock generation at reduced voltages has become a critical problem. Existing solutions often rely on auxiliary PLLs, replica DTCs, or complex analog calibration circuits, which increase design complexity, power, and area, and are not well suited for low-voltage operation. In this work, a fractional output divider architecture is proposed and implemented in 45-nm and 65-nm CMOS technology using the Tanner EDA tool, targeting reliable operation at a reduced supply voltage. The proposed design adopts a largely digital, open-loop clocking approach and incorporates DTC gain calibration, offset calibration, and foreground INL calibration to mitigate timing errors under low-voltage conditions. The novelty of this work lies in achieving effective DTC calibration without additional analog loops or auxiliary PLLs, making the design compact and power efficient. The system performance is evaluated through Tanner-based schematic design and T-Spice simulations, focusing on parameters such as power consumption, delay linearity, and jitter behaviour. Simulation results demonstrate acceptable clock quality suitable for SoC applications while achieving reduced power and area, validating the effectiveness of the proposed approach.
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A Low-Voltage Open-Loop Fractional Output Divider with Digital-to-Time Converter Calibration in 45-nm and 65-nm CMOS
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