Proposed abstract:
Camouflaged logic circuits are widely used in secure VLSI applications such as defence electronics, cryptographic processors, and intellectual property protection, where resistance to reverse engineering is critical. Threshold-voltage-based camouflaging techniques offer strong security without altering layout patterns, providing advantages such as invisibility to optical inspection and compatibility with standard CMOS processes; however, existing approaches often suffer from increased power consumption, large delay, complex dynamic circuitry, and area overhead. In current research, camouflaged gates based on dynamic threshold-voltage logic and threshold-defined switch designs have been demonstrated, but these methods introduce dynamic power overhead, leakage issues, or degraded performance due to weakly turned-on transistors. To address these limitations, this work proposes the development of a camouflage logic gate using a threshold-voltage-defined memory cell implemented in 45 nm CMOS technology, focusing on reducing power consumption, propagation delay, and silicon area while maintaining strong security against reverse engineering. The proposed design uses static CMOS logic combined with threshold-voltage-defined memory cells to select the intended logic function, eliminating dynamic pre charge operations and minimizing leakage current. In addition, the proposed camouflaged logic gate is extended to design key sequential circuits, including a data flip-flop and a shift register, demonstrating its suitability for practical digital system applications. The novelty of this work lies in integrating low-overhead camouflaged logic into both combinational and sequential circuits using a scalable 45 nm CMOS implementation. Performance evaluation is carried out through schematic design, layout implementation, and post-layout simulations using Tanner EDA tools, where parameters such as power consumption, delay, area, and leakage current are analysed and compared with conventional designs to validate the effectiveness of the proposed approach.
Software Implementation:
- Tanner EDA
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Design of Low Power Threshold Voltage Based Camouflaging Technique for Secure Combinational and Sequential VLSI Circuits
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