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Design and Application of Mean and Square Root Circuits for Stochastic Computing
Original price was: ₹25,000.00.₹12,000.00Current price is: ₹12,000.00.
Source : Verilog HDL
Base paper abstract:
Stochastic computing (SC) is an unconventional computing paradigm that represents values using probabilities. This representation enables simple logic gates to perform complex arithmetic operations. This brief proposes two low hardware-cost stochastic mean circuits for even and odd inputs, respectively, along with a high-accuracy stochastic square root circuit. The circuits are designed by considering correlation technique and achieve excellent performance. Experimental results demonstrate that the proposed mean circuits surpass previous counterparts in computing accuracy and hardware cost. For instance, the proposed 9-input mean circuit can achieve at least an 86.7% reduction in mean square error (MSE) and a 28.6% reduction in area. For the square root circuit, the proposed design achieves a reduction in MSE of at least 19.6%. The proposed circuits are further demonstrated with the Niblack binarization algorithm, which shows superior performance of accuracy. Index Terms: Stochastic computing, mean circuit, square root circuit, binarization processing.
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3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
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Proposed abstract:
Adaptive image binarization plays an important role in document analysis, medical imaging, surveillance systems, and embedded vision applications, where real-time and low-power processing are essential. Stochastic computing offers attractive advantages for such systems, including simple logic implementation, inherent fault tolerance, and reduced hardware complexity compared to conventional binary arithmetic. However, stochastic designs may suffer from accuracy degradation, longer bitstream latency, and correlation-induced errors, especially in window-based image processing algorithms such as Niblack thresholding. The main problem addressed in this work is the development of a compact and scalable stochastic architecture for 3×3 window-based Niblack binarization that achieves improved hardware efficiency without sacrificing image quality. Existing stochastic mean and square-root circuits either require large hardware overhead, multiple independent random number sources, or show increased error when scaling to multi-input window operations. Moreover, most reported implementations focus on larger window sizes and do not optimize FPGA resource utilization for small sliding-window architectures. To overcome these limitations, this work proposes a correlation-optimized 3×3 stochastic window architecture that employs shared random number generation, structured mean computation, and an efficient stochastic square-root unit integrated with an image line buffer technique. The novelty lies in combining correlation-aware arithmetic with a compact sliding window engine tailored for FPGA realization, enabling deterministic scalability and reduced resource consumption. Functional verification is performed using ModelSim to validate arithmetic correctness, while MATLAB GUI is used to evaluate image quality through PSNR and SSIM analysis. The complete design is synthesized and implemented using Xilinx FPGA tools, and hardware metrics such as slice LUTs, occupied slices, bonded IOBs, delay, and power consumption are analyzed to demonstrate area–delay–power efficiency compared to conventional implementations.
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A Correlation-Optimized 3×3 Stochastic Window Architecture for Hardware Efficient FPGA Based Niblack Binarization
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