Objective of this work:
- To develop stochastic computing architectures for 3×3 window operations using 8-bit pixel inputs.
- To design a scalable and deterministic SC architecture suitable for FPGA implementation with improved hardware efficiency.
- To design the Niblack algorithm using 3×3 window size and proved the performance with different image size. For the support we used Image line buffer technique and image convolution method.
- To functionally verify the proposed architecture using ModelSim simulation, ensuring correct arithmetic and logical behaviour, also analysis the Niblack image output in MATLAB GUI.
- To synthesize and implement the design using Xilinx FPGA tools, and evaluate hardware metrics including slice LUTs, occupied slices, bonded IOBs, delay, and power.
- To analyse scalability and performance of 3×3 window architectures with Niblack algorithm in terms of area, timing, and power consumption.
- To demonstrate that stochastic computing can be implemented efficiently and making it more practical for real-time FPGA-based image processing applications.
Proposed abstract:
Adaptive image binarization plays an important role in document analysis, medical imaging, surveillance systems, and embedded vision applications, where real-time and low-power processing are essential. Stochastic computing offers attractive advantages for such systems, including simple logic implementation, inherent fault tolerance, and reduced hardware complexity compared to conventional binary arithmetic. However, stochastic designs may suffer from accuracy degradation, longer bitstream latency, and correlation-induced errors, especially in window-based image processing algorithms such as Niblack thresholding. The main problem addressed in this work is the development of a compact and scalable stochastic architecture for 3×3 window-based Niblack binarization that achieves improved hardware efficiency without sacrificing image quality. Existing stochastic mean and square-root circuits either require large hardware overhead, multiple independent random number sources, or show increased error when scaling to multi-input window operations. Moreover, most reported implementations focus on larger window sizes and do not optimize FPGA resource utilization for small sliding-window architectures. To overcome these limitations, this work proposes a correlation-optimized 3×3 stochastic window architecture that employs shared random number generation, structured mean computation, and an efficient stochastic square-root unit integrated with an image line buffer technique. The novelty lies in combining correlation-aware arithmetic with a compact sliding window engine tailored for FPGA realization, enabling deterministic scalability and reduced resource consumption. Functional verification is performed using ModelSim to validate arithmetic correctness, while MATLAB GUI is used to evaluate image quality through PSNR and SSIM analysis. The complete design is synthesized and implemented using Xilinx FPGA tools, and hardware metrics such as slice LUTs, occupied slices, bonded IOBs, delay, and power consumption are analyzed to demonstrate area–delay–power efficiency compared to conventional implementations.
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A Correlation-Optimized 3×3 Stochastic Window Architecture for Hardware Efficient FPGA Based Niblack Binarization
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