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CNN_Analog_Kernel_Multiplication

Design of a Low-Power Analog Integrated Deep Convolutional Neural Network

Original price was: ₹12,000.00.Current price is: ₹8,000.00.

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Source : Verilog HDL

Base Paper Abstract:

In this article, a framework for the analog implementation of a deep convolutional neural network (CNN) is introduced and used to derive a new circuit architecture which is composed of an improved analog multiplier and circuit blocks implementing the ReLU activation function and the argmax operator. The operating principles of the individual blocks, as well as those of the complete architecture, are analysed and used to realize a low-power analog classifier, consuming less than 1.8 µW. The proper operation of the classifier is verified via a comparison with a software equivalent implementation and its performance is evaluated against existing circuit architectures. The proposed architecture is implemented in a TSMC 90-nm CMOS process and simulated using Cadence IC Suite for both schematic and layout design. Corner and Monte Carlo mismatch simulations of the schematic and the physical circuit (post layout) were conducted to evaluate the effect of transistor mismatches and process voltage temperature (PVT) variations and to showcase a proposed systematic method for offsetting their effect.

List of the following  materials will be included with the Downloaded Backup:

1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Existing and Proposed Project Comparison with output video 
3. Basic Documentation (20 to 30 Pages):
3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
4. Online Support ( Any Desk / Zoom / Google Meet)

 

Improvement of this project:

  • To develop the soft-decision circuit of the analogue multiplier along with the signed sigmoid circuit using 45 nm CMOS technology.

  • To develop the 3×3 array soft-decision circuit architecture for CNN kernel multiplication using 45 nm CMOS technology and compare the parameters in terms of area, power, and delay.

  • To reduce the area and power consumption and minimise the interconnection and use minimal transistors.

Software Implementation:
  • Tanner EDA

” Thanks for Visit this project Pages – Buy It Soon “

Low power Analog Signed Sigmoid and Soft-Decision Kernel Multiplication for CNN application

 

Terms & Conditions:

  • Customer are advice to watch the project video file output, before the payment to test the requirement, correction will be applicable.
  • After payment, if any correction in the Project is accepted, but requirement changes is applicable with updated charges based upon the requirement.
  • After payment the student having doubts, correction, software error, hardware errors, coding doubts are accepted.
  • Online support will not be given more than 3 times.
  • On first time explanations we can provide completely with video file support, other 2 we can provide doubt clarifications only.
  • If any Issue on Software license / System Error we can support and rectify that within end of the day.
  • Extra Charges For duplicate bill copy. Bill must be paid in full, No part payment will be accepted.
  • After payment, to must send the payment receipt to our email id.
  • Powered by NXFEE INNOVATION, Pondicherry.

 

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CNN_Analog_Kernel_Multiplication Design of a Low-Power Analog I...

Original price was: ₹12,000.00.Current price is: ₹8,000.00.

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