Objectives of the Proposed Work

1. To design and implement a fail-safe architecture for FPGA-based systems that detects functional, routing, and configuration memory faults and forces the system into a defined safe state.
2. To develop the Dynamic Partial Reconfiguration (DPR) region entirely in Verilog HDL (Verilog-2001 style), ensuring synthesizability and compatibility with Xilinx Vivado design flows.
3. To integrate two redundant instances of a cryptographic processing core (e.g., AES) inside the DPR region, operating synchronously with identical inputs to enable duplication-with-comparison (DWC).
4. To design and implement DEFCON-based fail-safe monitors in Verilog HDL, capable of detecting mismatches in both internal datapath registers and output interfaces of the redundant cores.
5. To exploit the dual-output structure of FPGA LUTs at the RTL and synthesis level, enabling compact and resource-efficient realization of redundant XOR and OR comparison logic.
6. To ensure self-checking capability of the monitoring circuitry, such that faults occurring inside the DEFCON monitors themselves are detectable and do not mask functional-unit faults.
7. To implement hierarchical alarm generation and compression logic, producing multiple independent alarm signals that guarantee fault detection under single-fault and selected dual-fault conditions.
8. To design a fail-safe output blocking mechanism, which forces DPR outputs to a predefined safe value when any alarm condition is asserted.
9. To enable controlled partial reconfiguration of the DPR region, allowing faulty logic to be reloaded or refreshed without disrupting the static region of the FPGA.
10. To integrate the DPR region with a static control interface, enabling configuration, data transfer, and alarm monitoring through GPIO or AXI-compatible signals.
11. To synthesize, implement, and verify the complete design on a Xilinx Artix-7 FPGA using Vivado, ensuring correct timing, placement, and routing under DPR constraints.
12. To evaluate resource utilization, timing performance, and power overhead introduced by the DEFCON-based fail-safe architecture compared to an unprotected design.
13. To validate fault detection behavior through simulation-based fault injection, including datapath faults and configuration-related fault scenarios.
14. To demonstrate safe system behavior under detected fault conditions, ensuring that no corrupted or unauthorized data propagates beyond the DPR region.
15. To establish a reusable Verilog HDL framework for fail-safe DPR-based FPGA designs, suitable for future safety-critical and security-critical applications.