Objectives of the Proposed Work
- To design and implement a fail-safe architecture for FPGA-based systems that detects functional, routing, and configuration memory faults and forces the system into a defined safe state.
- To develop the Dynamic Partial Reconfiguration (DPR) region entirely in Verilog HDL (Verilog-2001 style), ensuring synthesizability and compatibility with Xilinx Vivado design flows.
- To integrate two redundant instances of a cryptographic processing core (e.g., AES) inside the DPR region, operating synchronously with identical inputs to enable duplication-with-comparison (DWC).
- To design and implement DEFCON-based fail-safe monitors in Verilog HDL, capable of detecting mismatches in both internal datapath registers and output interfaces of the redundant cores.
- To exploit the dual-output structure of FPGA LUTs at the RTL and synthesis level, enabling compact and resource-efficient realization of redundant XOR and OR comparison logic.
- To ensure self-checking capability of the monitoring circuitry, such that faults occurring inside the DEFCON monitors themselves are detectable and do not mask functional-unit faults.
- To implement hierarchical alarm generation and compression logic, producing multiple independent alarm signals that guarantee fault detection under single-fault and selected dual-fault conditions.
- To design a fail-safe output blocking mechanism, which forces DPR outputs to a predefined safe value when any alarm condition is asserted.
- To enable controlled partial reconfiguration of the DPR region, allowing faulty logic to be reloaded or refreshed without disrupting the static region of the FPGA.
- To integrate the DPR region with a static control interface, enabling configuration, data transfer, and alarm monitoring through GPIO or AXI-compatible signals.
- To synthesize, implement, and verify the complete design on a Xilinx Artix-7 FPGA using Vivado, ensuring correct timing, placement, and routing under DPR constraints.
- To evaluate resource utilization, timing performance, and power overhead introduced by the DEFCON-based fail-safe architecture compared to an unprotected design.
- To validate fault detection behavior through simulation-based fault injection, including datapath faults and configuration-related fault scenarios.
- To demonstrate safe system behavior under detected fault conditions, ensuring that no corrupted or unauthorized data propagates beyond the DPR region.
- To establish a reusable Verilog HDL framework for fail-safe DPR-based FPGA designs, suitable for future safety-critical and security-critical applications.
Proposed abstract:
Fail-safe architectures are increasingly required in safety-critical and security-critical FPGA applications such as cryptographic accelerators, automotive controllers, and industrial control systems, where any fault must be detected and the system must transition into a known safe state rather than continue operation. These architectures offer strong protection against configuration memory upsets, routing faults, and malicious fault injection attacks, but they typically suffer from increased area overhead, complex monitoring logic, and limited support for runtime recovery. Existing FPGA-based solutions mainly rely on triple modular redundancy or basic duplication-with-comparison techniques, which either incur high resource costs or lack self-checking capability within the monitoring circuitry itself. Moreover, many prior works validate fail-safe concepts using abstract FPGA models or SoC-based platforms, with limited evidence of full Verilog-based dynamic partial reconfiguration implementation on low-cost standalone FPGAs. To address these limitations, this work proposes a complete DEFCON-inspired fail-safe architecture implemented entirely in synthesizable Verilog HDL using a dynamic partial reconfiguration region on an Artix-7 FPGA. Two redundant instances of an AES-128 cryptographic core operate synchronously within the DPR region, while compact self-checking monitors detect mismatches in internal datapath registers and output interfaces. The proposed solution exploits the dual-output structure of FPGA LUTs to realize resource-efficient redundant XOR and OR comparison logic, ensuring that faults within the monitoring circuitry itself do not mask functional faults. A hierarchical alarm generation and compression network guarantees reliable fault detection under single-fault and selected dual-fault conditions, and a fail-safe output blocking mechanism enforces a predefined safe output state. The novelty of this work lies in the practical realization of a reusable, Verilog-only fail-safe DPR framework on a standalone FPGA with quantified timing, area, and power results. The design is synthesized and implemented using Xilinx Vivado, achieving timing closure with positive slack, low resource utilization, and modest power consumption, thereby demonstrating the feasibility and effectiveness of the proposed architecture for real-world fail-safe FPGA systems.
Software Implementation:
- Modelsim
- Xilinx
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Design and Implementation of a DEFCON-Based Fail-Safe Architecture for DPR-Enabled FPGA Cryptographic Systems
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