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10T-SRAM Cell for AES Systems

Full-Array Boolean Logic CIM Macro with Self-Recycling 10T-SRAM Cell for AES Systems

Original price was: ₹12,000.00.Current price is: ₹6,000.00.

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Source : Tanner EDA

Base Paper Abstract:

Computing in memory (CIM), which alleviates the need to transfer a large amount of data between processor and memory, significantly reducing latency and energy consumption, is a promising new computing architecture for addressing the von Neumann bottleneck problem. This article proposes a CIM array structure composed of self-recycling 10T static random access memory (SRAM) cells, which can realize orthogonal data writing, and multiple Boolean logical operations for the entire array. The self-recycling and full-array activation characteristics are extremely suitable for accelerating diverse data processing algorithms such as the Advanced Encryption Standard (AES). A 4-kb SRAM is implemented in 55-nm CMOS technology to verify the effectiveness of the design. Compared with other state-of-threat architectures, the throughput and the operating frequency of the proposed CIM macro are increased to 843 GOPS/kb (2.64×) and 823.7 MHz (2.6×), respectively. The energy efficiency reaches 246.9 TOPS/W. When applied to the AES, the energy consumption is 35.77% less than the digital CIM architecture that is not self-recycling.

List of the following  materials will be included with the Downloaded Backup:

1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Existing and Proposed Project Comparison with output video 
3. Basic Documentation (20 to 30 Pages):
3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
4. Online Support ( Any Desk / Zoom / Google Meet)

 

Improvement of this project:

  • Developed a single bit 10T SRAM design by using 45nm CMOS technology.
  • Developed a OR gate, XOR gate, and AND gate design using this SRAM Operations
  • Developed 8×8 array of SRAM architecture by using 45nm CMOS technology and comparing the parameter in term of Area, Delay and power consumption.
Software Implementation:
  • Tanner EDA

” Thanks for Visit this project Pages – Buy It Soon “

Design and Analysis of 45nm CMOS-Based 10T-SRAM Computing-in-Memory Macro with AND, OR, XOR based Boolean Operations for AES Applications

 

Terms & Conditions:

  • Customer are advice to watch the project video file output, before the payment to test the requirement, correction will be applicable.
  • After payment, if any correction in the Project is accepted, but requirement changes is applicable with updated charges based upon the requirement.
  • After payment the student having doubts, correction, software error, hardware errors, coding doubts are accepted.
  • Online support will not be given more than 3 times.
  • On first time explanations we can provide completely with video file support, other 2 we can provide doubt clarifications only.
  • If any Issue on Software license / System Error we can support and rectify that within end of the day.
  • Extra Charges For duplicate bill copy. Bill must be paid in full, No part payment will be accepted.
  • After payment, to must send the payment receipt to our email id.
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10T-SRAM Cell for AES Systems Full-Array Boolean Logic CIM M...

Original price was: ₹12,000.00.Current price is: ₹6,000.00.

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