Deploying deep neural networks (DNNs) on those resource-constrained edge platforms is hindered by their substantial computation and storage demands. Quantized multiprecision DNNs (MP-DNNs), denoted as MP-DNNs, offer a promising solution for these limitations but pose challenges for the existing RISC-V processors due to complex instructions, suboptimal parallel processing, and inefficient dataflow mapping. To tackle the challenges mentioned above, SPEED, a scalable RISC-V vector (RVV) processor, is proposed to enable efficient MP-DNN inference, incorporating innovations in customized instructions, hardware architecture, and dataflow mapping. First, some dedicated customized RISC-V instructions are introduced based on RVV extensions to reduce the instruction complexity, allowing SPEED to support processing precision ranging from 4- to 16-bit with minimized hardware overhead. Second, a parameterized multiprecision tensor unit (MPTU) is developed and integrated into the scalable node architecture to enhance flexibility and scalability by providing reconfigurable parallelism that matches the computation patterns of diverse MP-DNNs. Third, a flexible mixed dataflow method is adopted to improve computational and energy efficiency according to the computing patterns of different DNN operators. The synthesis experiments carried out on TSMC 28-nm technology. Experimental results show that SPEED achieved a peak throughput of 737.9 GOPS and an energy efficiency of 138.4 GOPS/W for 8-bit operator. Furthermore, SPEED exhibits superior area-efficiency compared with other RVV processors, with the enhancements of 5.9%–26.9× and 8.2%–18.5× for 8-bit operator and tensor performance, respectively, which highlights SPEED’s significant potential for efficient MP-DNN inference.
Index Terms —
Deep neural networks (DNNs), DNN processor, multiprecision, RISC-V, vector processor.
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