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DiP: A Scalable, Energy-Efficient Systolic Array for Matrix Multiplication Acceleration
Original price was: ₹18,000.00.₹10,000.00Current price is: ₹10,000.00.
Source : Verilog HDL
Base paper abstract:
Transformers are gaining increasing attention across Natural Language Processing (NLP) application domains due to their outstanding accuracy. However, these data-intensive models add significant performance demands to the existing computing architectures. Systolic array architectures, adopted by commercial AI computing platforms like Google TPUs, offer energy-efficient data reuse but face throughput and energy penalties due to input-output synchronization via First-In-FirstOut (FIFO) buffers. This paper proposes a novel scalable systolic array architecture featuring Diagonal-Input and Permutated weight stationary (DiP) dataflow for matrix multiplication acceleration. The proposed architecture eliminates the synchronization FIFOs required by state-of-the-art weight stationary systolic arrays. Beyond the area, power, and energy savings achieved by eliminating these FIFOs, DiP architecture maximizes the computational resource utilization, achieving up to 50% throughput improvement over conventional weight stationary architectures. Analytical models are developed for both weight stationary and DiP architectures, including latency, throughput, time to full PEs utilization (TFPU), and FIFOs overhead. A comprehensive hardware design space exploration using 22nm commercial technology demonstrates DiP’s scalability advantages, achieving up to a 2.02× improvement in energy efficiency per area. Furthermore, DiP outperforms TPU-like architectures on transformer workloads from widely-used models, delivering energy improvement up to 1.81× and latency improvement up to 1.49×. At a 64×64 size with 4096 PEs, DiP achieves a peak throughput of 8.192 TOPS with energy efficiency 9.548 TOPS/W.
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3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
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Proposed abstract:
Matrix multiplication and systolic array architectures are widely used in modern computing applications such as artificial intelligence, digital signal processing, image processing, cryptography, and high-performance embedded systems. These architectures provide advantages such as regular data flow, high parallelism, and efficient hardware utilization, making them suitable for FPGA and VLSI implementations. However, conventional systolic array multipliers still face several challenges including increased logic utilization, higher power consumption, and complex arithmetic units such as conventional full adders used in processing elements. These limitations affect scalability and energy efficiency when implementing large matrix multiplications on FPGA platforms. Many existing works focus on optimizing matrix multiplication architectures using systolic arrays, pipeline techniques, and hardware accelerators, but most designs still rely on traditional adder structures that increase the hardware area and switching power. To address these issues, this work proposes the design of an 8×8 sliding function based systolic array architecture using array multiplication to achieve efficient matrix multiplication with improved hardware efficiency. The proposed architecture introduces an XOR–MUX based arithmetic structure in place of the conventional full adder to reduce logic complexity and power consumption in the processing elements of the systolic array. The novelty of the proposed work lies in integrating a sliding data movement mechanism with a lightweight XOR–MUX arithmetic design, which reduces logic resource usage while maintaining correct multiplication functionality. The proposed design is implemented and evaluated using the Xilinx Vivado design suite targeting the Artix-7 FPGA platform. Performance evaluation is carried out in terms of logic utilization, power consumption, and computational efficiency, and the results are compared with conventional systolic array designs using full adders. The experimental results demonstrate that the proposed architecture achieves reduced logic size and lower power consumption while maintaining efficient parallel computation for matrix multiplication.
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Design and FPGA Implementation of an 8×8 Sliding Function Based Systolic Array Using Array Multiplication With XOR–MUX Based Low-Power Architecture
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