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Source : VHDLAbstract:
In this paper, we propose a low-power technique, called RF power gating, which consist in varying the active time radio (ATR) of the RF front end at a symbol time scale. This technique is especially well suited to adapt the power consumption of the receiver to the performance needs without changing its architecture. The effect of this technique on the bit error rate (BER) performance is studied for a basic estimator in the specific case of Binary shift keying signaling (BPSK). In existing it Minimum shift keying signaling will used in RF Power gating technique, it will have, low efficiency, and more bit error rate. In this paper to modified the Minimum shift keying technique to Binary shift keying technique, and shown the BER results and the energy model are finally merged to determine the best ATR meeting the design constraints. Finally this work is implemented in VHDL, and synthesized with Xilinx FPGA Vertex-5, and shown the area, power and delay reports.
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