Proposed abstract:

Operational trans conductance amplifiers (OTAs) are widely used in sensor interfaces, biomedical circuits, switched-capacitor systems, data converters, and low-power communication blocks because they offer high linearity, tuneable trans conductance, and compatibility with advanced CMOS processes. While modern technology nodes provide advantages such as reduced chip area, higher intrinsic speed, and lower supply voltages, they also introduce disadvantages including reduced intrinsic gain, increased leakage, and tighter design margins. These challenges motivate the need for improved amplifier architectures capable of maintaining high gain and low power consumption in deeply scaled CMOS. Existing OTAs in advanced nodes typically rely on cascading, gain boosting, or multi-stage compensation, but these methods increase circuit complexity and power, and often lose efficiency at low supply voltages. To address these issues, this work proposes the design and comparative analysis of a two-stage CMOS OTA implemented in 45-nm and 22-nm technology nodes, targeting enhanced intrinsic gain with minimal power consumption. The approach focuses on optimized transistor sizing, low-voltage bias strategies, and compensation techniques inspired by recent advancements in stable two-stage amplifiers, such as zero-tracking and improved Miller compensation, as observed in recent literature and device behaviour trends. The novelty of this work lies in demonstrating how advanced-node short-channel effects can be exploited rather than mitigated, using device parameters to enhance gain while preserving low-power operation across both technology options. Performance metrics including dc gain, unity-gain bandwidth, phase margin, output swing, offset, and total power consumption are evaluated through Cadence Virtuoso and Spectre simulations, with additional verification using MATLAB-based analytical models for consistency across scenarios.

Software Implementation:

• Tanner EDA

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A Low-Power Two-Stage CMOS OTA in 22 nm and 45 nm Technologies with Enhanced Gain and Power Efficiency