Proposed abstract:
Digital signal processing, image processing, and neural network acceleration widely rely on high-speed multiplication, where approximate computing has emerged as an effective approach to improve energy efficiency and throughput. Approximate multipliers offer clear advantages in terms of reduced power consumption, smaller area, and faster operation; however, they also introduce challenges such as unbalanced error distribution, increased latency in accumulation stages, and performance degradation due to inefficient adder structures. The primary problem addressed in this work is the delay and hardware complexity caused by conventional adders used in hybrid approximate multiplier architectures, which limits their effectiveness on FPGA platforms. Existing approaches mainly focus on approximation at the arithmetic level, such as logarithmic or partial-product-based designs, but often neglect optimization of the carry propagation and accumulation logic, resulting in suboptimal delay and power performance. To overcome these limitations, this work proposes a hybrid approximate multiplier architecture that integrates a carry select adder implemented using an XOR–MUX-based full adder to reduce carry propagation delay and overall circuit complexity. The key novelty of the proposed design lies in combining approximation-aware multiplication with a low-latency, hardware-efficient adder structure, enabling improved speed without significantly affecting computational accuracy. The proposed architecture supports signed arithmetic operations and is well suited for error-tolerant applications in FPGA-based systems. The design is described using Verilog HDL, functionally verified in ModelSim, and synthesized on a Xilinx Virtex-5 FPGA platform. Performance evaluation is carried out in terms of lookup table utilization, slice registers, critical-path delay, and power consumption, demonstrating noticeable improvements over existing hybrid approximate multiplier designs, thereby ensuring enhanced performance, energy efficiency, and reliable operation.
Software Implementation:
- Modelsim
- Xilinx
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Design of an Efficient Hybrid Approximate Multiplier Employing XOR-MUX-Based Carry Select Adder for Reduced Latency and Complexity
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