Proposed abstract:

Static random-access memory (SRAM) is widely used in aerospace, defence, medical electronics, and other radiation-prone applications because of its high speed, low latency, and low operating voltage. However, as device dimensions’ shrink in advanced CMOS technologies, conventional SRAM cells become increasingly sensitive to radiation-induced soft errors, offering advantages in density and speed but suffering from disadvantages such as reduced node charge, higher upset probability, and limited self-recovery capability. Existing radiation-hardened SRAM cells, including RHD12, QCCM12T, QUCCE12T, RHMD10T, SEA14T, RHM-12T, S4P8N, S8P4N, RH-14T, HRLP16T, CC18T, and RHM, provide improved protection from single-node and double-node upsets but still show drawbacks such as higher power consumption, larger delay, or limited recovery of DNU pairs. To address these challenges, this work designs and compares all these hardened cells using 22 nm CMOS technology, identifying their strengths and limitations in terms of delay, power, and area. Building on these findings, two new SRAM architectures, S6P8N and S8P6N, are designed to enhance soft-error tolerance without adding structural complexity. The proposed cells use optimized transistor placement and redundancy to achieve full recovery from all single-node upsets and 67% recovery of double-node upset cases, while also reducing average power in S6P8N and improving read and write speed in S8P6N. The novelty of this work lies in achieving a balanced improvement in reliability, speed, and power efficiency compared to existing state-of-the-art hardened designs. All SRAM cells, including the proposed ones, are developed, simulated, and evaluated using Tanner EDA tools under 22 nm CMOS technology files. Performance is analysed through power, delay, area, read access time, write access time, static noise margin, and Monte-Carlo simulation results, confirming that the proposed S6P8N and S8P6N architectures offer a strong and scalable solution for next-generation radiation-tolerant memory systems.

Software Implementation:

• Tanner EDA

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Radiation-Tolerant SRAM Design with Enhanced Self-Recovery Using S6P8N and S8P6N Architectures in 22 nm CMOS Technology