Improvement:

• To develop an approximate floating point divider.
• Implementation of the truncation design in order to reduce the use of larger hardware.
• Implementation of small LUT for coefficients and carry-save adder block instead of complex multipliers.
• Development of the Full adder and Full Subtraction using the XOR gate and 2:1 MUX in order to reduce the area and delay.
• Finally developed this work in Verilog HDL and compared all the parameters in terms of area, delay and power.

Proposed Title:

Low Power Approximate Floating Point Divider using Truncation and Optimised XOR-MUX based Arithmetic Units

Proposed Abstract:

Floating point division is a critical operation in many applications such as image processing, signal processing, scientific computing, and neural network accelerators, where accuracy and speed are essential but hardware resources and power consumption become major concerns. Conventional floating point dividers achieve high precision but suffer from large area, high delay, and increased power usage, making them less suitable for recent applications. Several existing approaches such as iterative algorithms, reciprocal-based methods, and logarithmic techniques have been explored to reduce complexity, but these still involve multipliers, large look-up tables, or deeper pipeline stages that add to hardware cost. To address these limitations, this work proposes an approximate floating point divider architecture that combines truncation, small LUT-based coefficient storage, and a carry-save adder block to simplify the design and reduce computation overhead. Further, this improvement is achieved by developing optimized XOR-MUX based full adders and subtractions, which significantly minimize area, delay and power, when compared with conventional arithmetic units. The novelty of this design lies in replacing complex multipliers with lightweight logic structures while maintaining acceptable accuracy, thus achieving an effective trade-off between performance and resource utilization. The proposed divider is described and verified in Verilog HDL, synthesized, and evaluated in terms of area, power, and delay metrics. Results show that the design achieves considerable reduction in hardware complexity and power consumption while sustaining reasonable precision, demonstrating its suitability for energy-efficient digital systems and approximate computing applications.