₹12,000.00Original price was: ₹12,000.00.₹8,000.00Current price is: ₹8,000.00.
Source : TANNER EDA
Abstract:
This paper presents a 6-GS/s 6-bit time-interleaved successive approximation register (SAR) analog to digital converter (ADC) realized in 90-nm CMOS. The ADC consists of 32 single SAR-ADCs. The measured effective-number-of-bits (ENOB) at sampling rate of 6.144 GS/s are 5-bit at DC and 3.6-bit at the Nyquist frequency. The power consumption of the ADC-core without I/O’s and 4-to-1 output MUX is 359 mW for an input swing of 1 V peak to peak differential, resulting in a FOM of 4.9 pJ/conv. The proposed design of this Successive approximation register analog to digital converter in Tanner EDA at 65-nm technology and finally proved the comparison of area, power and delay.
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