Proposed Title :

FPGA Design of 4:2, 5:2, and 7:2 Compressor Used in Error-Resilient Approximate Multiplier for Error Compensation

Improvement of this project :

• To design the Proposed Multiplier 1 and Proposed Multiplier 2 architecture using number of proposed approximate compressors and proved the performances.

• To design the EEG signal based FIR Filter design which using Proposed Multiplier 1 and Proposed Multiplier 2, and analysis the performance of area, delay and power.

• To develop this work in front end design of FPGA Implementation using Verilog HDL.

Software Implementation:

• Modelsim
• Xilinx

Proposed System:

Electroencephalogram (EEG) is a form of cardiovascular measurement and dynamic information from the Brain conditions. However, numerous noises usually harm the amplitude and time period of the signal from the EEG signal, at following a transition of the analog EEG signal from the sensor module into a digital format. The appropriate digital filter may be used to remove different forms of noise such as Baseline Wander, Power line interference, High frequency noise and Physiological Artifacts. The Digital FIR filter will have prospected to reduce the artifacts in the EEG signals. This Digital FIR filter can have more performance by using 8 TAP numbers such as multiplying, delaying and getting more effectiveness. This proposed work would implement a 1 norm minimization in the FIR filter with liner step method to minimize sparse complexity and reduce the mini-max approximation error for sparse maximization. This proposed work of Digital FIR filter, which developed using two different Approximate computing multiplier to reducing power consumption and design complexity. Given these facts, several rules for selecting indicators of potential zero coefficients to be used in 1 standard optimization are adopted in the proposed algorithm. The efficacy of the proposed design algorithm was developed in Verilog HDL, simulated and synthesized in Vivado Zynq FPGA, and finally prove all the parameters in terms of area, delay and power.

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Two Efficient Approximate Unsigned Multipliers by Developing New Configuration for Approximate 4:2 Compressors