Objective:

• To design a high-throughput FPGA-based random number generator that uses metastability for true randomness and a lightweight PRPG to increase the output rate.
• To adapt a truncation-aware PRPG originally developed for SSM approximate multiplier testing and repurpose it as an entropy expansion mechanism seeded by true random sources.
• To investigate and compare nonlinear entropy mixing techniques, specifically an SSM-based multiplier with MAC and a Truncation multiplier with MAC, within a TRNG–PRPG system.
• To reduce hardware cost and critical path delay of the random number generator while maintaining power efficiency and scalability on FPGA platforms.
• To implement and validate the proposed architecture using industry-standard tools, with functional verification in ModelSim and post-synthesis evaluation in Xilinx Vivado.
• To demonstrate the suitability of truncation-based nonlinear mixing for high-speed random number generation, showing improved area and timing performance compared to SSM-based approaches.

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A Hybrid TRNG PRPG Architecture for Resource Efficient Static Segment and Truncation Multiplier Based Random Pattern Generation