Source Code : VHDL

Abstract:
We propose a low-power content-addressable memory (CAM) employing a new algorithm for associativity between the input tag and the corresponding address of the output data of 128bit. The proposed architecture is based on a recently developed sparse clustered network using binary connections that on-average eliminates most of the parallel comparisons performed during a search. Therefore, the dynamic energy consumption of the proposed design is significantly lower compared with that of a conventional low-power CAM design. Given an input tag, the proposed architecture computes a few possibilities for the location of the matched tag and performs the comparisons on them to locate a single valid match. A design methodology based on the silicon area and power budgets, and performance requirements is discussed. The proposed architecture of this paper will be analysis the logic size, area and power consumption using Xilinx 14.2.

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