An Ultra-Low Leakage and Wide-Range Voltage Level Shifter for Low-Power Digital CMOS VLSIs

Improvement of this project:

• To develop a low leakage level shifter in 45 nm technology and reduce the area, delay and power consumption.
• To design the 7 different Level Shifter architecture is given in the paper of Fig.3 Proposed LS and the Fig.2 LS design architecture at 45 nm and prove the performance evaluations of Area, delay and power.
• Implementation of the leakage-optimized transistors reduce energy per transition which provide energy efficiency.
• Implementation of the Level shifter that enhances robustness for low-power applications.
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