BASED on the recent progress in CMOS process scaling, time resolution is becoming more and more superior to voltage resolution due to the high-speed transistors and the reduced supply voltage , . Recently, a time-to-digital converter (TDC) has been used for various applications, e.g., ADPLLs, space science instruments, jitter measurements, and so on. In particular, with the recent improvement in TDC performance, it is often used in high-precision time-of-flight measurement applications, such as laser range finder  and mass spectrometry . It is also used in fluorescence lifetime imaging applications . In these applications, which are the main target applications of this paper, fine time resolution and wide dynamic range are demanded at the same time . Since the TDC determines the overall performance of the measurement, a few ps time resolution with low jitter at a sampling rate of several MS/s is often requested.
Sampling rate of several MS/s is often requested. In terms of fine resolution, several time conversion techniques that realize sub-gate-delay resolution have been proposed. A Vernier TDC is widely adopted, thanks to the simplicity of its design concept –. As illustrated in Fig. 1, a typical Vernier TDC needs two independent delay lines that are often implemented as ring delay lines to save area. Two lines have different delay steps, e.g., t1 and t2 (t2 < t1), and thus, the initial time interval Tin between two rising transitions gradually shrinks until the moment when the transition in lower delay line catches up with that in the upper one. By tuning the delay difference TLSB = t1−t2, we can realize fine time resolution. However, this architecture requires two independent delay lines, where mismatch between them is inevitable.
On the other hand, a pulse-shrinking (PS) TDC shown in Fig. 2, which is also a type of Vernier TDCs, utilizes the delay difference between rising and falling transitions of a buffer instead of the two independent delay lines , . The buffer is intentionally designed to have different rise and fall delays, e.g., tr and t f (t f < tr), and thus, the incoming pulsewidth shrinks TLSB = tr − t f by propagating through each buffer stage until it disappears. Unlike Vernier TDCs.
PS TDC is realized with a single delay line that amounts to less area and power. It also alleviates the mismatch issue because both rising and falling transitions propagate the same way on the layout. The typical PS TDC, however, has to treat the input time interval as a pulse, which could be impossible for a few ps time interval input . It also has difficulty in resolving the narrow input pulse with fine resolution because the PS rate becomes nonuniform, as shown in Fig. 3, when its width shrinks narrower than a certain threshold Tth, which is roughly equal to the sum of signal transition times for the buffer output to fully swing from low to high and from high to low . Though the conventional PS TDC can be used with a fixed offset pulsewidth to keep the input pulse sufficiently wide to accept the fine time difference, it wastes time and power to wait for the conversion of the offset part and it also integrates extra jitter. Due to these drawbacks, the PS TDCs have been used only for limited applications that request a coarse time resolution, i.e., several tens of ps.
The architecture of the TDCs discussed so far focused on fine time resolution. However, for a wide dynamic range, it may become unattractive. For example, a Vernier TDC that has an N-bit and τ time resolution uses 2N delay elements and has τ × 2N dynamic range. If the time resolution τ is reduced by half, the dynamic range is also halved. Then, to keep the same dynamic range, the TDC requires additional 2N delay elements that increase area occupation, slow down conversion rate, and increase jitter accumulation as N becomes larger. A looped TDC architecture is one of the simplest ideas to extend the dynamic range while preventing area increase . A loop counter determines how many times the start signal rotates on the loop until the stop signal catches up. The overall conversion result can be calculated from the counter output and the thermometer code provided by the DFFs. In an ideal situation the input range can be expanded infinitely just by adding more bits in the counter. However, the issues on the conversion rate and jitter accumulation have not been solved.
For long time interval measurements, the conversion time and jitter accumulation can be reduced by a two-step (TS) approach depicted in Fig. 4. The TS TDC is composed of two TDCs: one has a coarse time resolution and wide range (a coarse TDC) and the other has a fine resolution and narrow range (a fine TDC). Though the concept of TS architecture is simple, it actually has many possible difficulties in practice . First, the multiplexer between two stages introduces unwanted delay in the signal propagation path. To compensate this delay, a replica delay has to be inserted in the stop signal path and has to be carefully tuned to match with the delay of the multiplexers. These additional delay elements lead to difficulty in delay tuning and also cause jitter accumulation. Second, transferring the time residue to the fine TDC itself is challenging because the layout of the propagation paths between two TDCs has to be symmetric for any input time interval to avoid nonlinearity caused by difference in propagation delays. Thus, the conventional TS TDC has an inevitable nonlinearity caused by this inter-stage signal propagation, which is not perfectly symmetric in reality. Moreover, the TS architecture requires the ratio between the time resolutions of the two TDCs to combine the quantization results. Although this ratio can be determined to some extent at the design stage, it is not actually the same as that in the fabricated design due to process, voltage, and temperature variations. Therefore, some techniques to calibrate this mismatch are needed.
In this paper, in order to achieve a fine resolution and wide range at the same time, we employ a sub-gate-delay resolution PS architecture as the fine TDC of the TS architecture and propose several techniques to overcome the issues in the conventional PS and TS TDCs discussed so far. The proposed PS TDC incorporates a novel pulse injection with a built-in offset pulse and always keeps the propagating pulse wider than the offset one. Then, the PS TDC finishes the conversion process when it detects the original offset pulse width that is set wider than the threshold Tth to avoid the non-uniform PS rate issue, as shown in Fig. 3 . Based on this scheme, the PS TDC realizes a fine time resolution, avoids unneeded jitter accumulation, and saves conversion time and power consumption, while it inherits the advantages of the conventional PS TDC architecture. The proposed TS TDC avoids the use of the inter-stage multiplexer and overcomes the resolution mismatch issue with a built-in coarse gain calibration mechanism so that the proposed TS TDC realizes a wide dynamic range and a fine time resolution at the same time.
- High power and low density.
- High area, power and delay.
- Hardware complicity is more.
In recent design of CMOS technology will increases efficiency in all domain, such as signal processing, image processing, digital arithmetic applications and so on. Here in this paper presents a CMOS implementation with signal processing method of time to digital converter, it will focus on wide range in two step and fine resolution of pulse shrinking method with compared to existing pulse shrinking method. Here this TS ( two-step) TDC ( Time to digital converter) will present in 16-bit rage of 2.0ps resolution and given a supply voltage to 1.8V. Finally this method will developed in 45nm and 180nm of CMOS technology with built in coarse gain calibration. This proposed architecture of PSBR ( Pulse shrinking buffer ring) will designed using GDI (Gate Diffusion input) method to reduce the MOSFET’S, area and power. This method will compared and proved in all the terms of area, delay and power.
The block diagram of the fine-stage TDC based on PS buffer ring (PSBR) is illustrated in Fig. 5. It is mainly composed of 2N-stage PS buffers (PSBs). The output of kth PSB (k = 0,…, N − 1) is connected to both a data input of kth DFF and a clock input of (N + k)th DFF, while the output of (N + k)th PSB on the opposite side of the ring is connected to both a data of (N + k)th and a clock of kth DFFs. Besides, the outputs of (N −1)th and (2N −1)th PSBs are connected to counters outside the PSBR core. The PSB has three functions: suspending the transition of the input signal, forcing the output at low or high level, and shrinking an input pulsewidth; in other words, the falling edge propagates the PSB faster by TLSB than the rising edge. To realize these functions, the PSB circuit in Fig. 6 is used. The leftmost transmission gate is used to suspend a signal propagation when it is OFF, and the neighboring reset transistors force the output of PSB at low or high level. INV1 in the PSB is designed with a wider pMOS than that of INV2 so that the PSB falling transition delay t f becomes smaller than the rising transition delay tr, hence an input pulse shrinks its width through these inverters. The ratio of these two pMOS widths determines TLSB. Some dummy transistors are also integrated to keep symmetry of the circuit.
When the PSBR is in its standby state, zeroth and Nth PSBs suspend the signal propagation and force their outputs at low and high levels, respectively. Other PSBs enable the signal propagation so that the ring keeps the outputs of the zeroth to (N − 1)th PSBs at low level and those of Nth to (2N − 1)th PSBs at high level, as indicated in Fig. 5. The rise transition of IN1 input subsequently enables the signal propagation at zeroth PSB, and it triggers the rising edge propagation from (2N −1)th to zeroth PSB outputs. After Tin, the rise transition of IN2 triggers the falling edge propagation from (N −1)th to Nth PSB outputs. Note that the first falling transition arrives at zeroth PSB after propagating N PSBs. Therefore, the time difference between the falling edges at Nth and zeroth PSBs is equal to the total falling propagation delay of N PSBs, which works as a built-in offset pulsewidth and is defined as Toffset = N × t f . Through this time difference injection scheme, the input Tin is fed into the ring in addition to the built-in Toffset, as shown in Fig. 7, where the width of the pulse signal in the ring just after IN2 injection is a sum of Tin and Toffset . Thus, this scheme allows a tiny input time interval injection because it does not directly translate it into a narrow pulse.
Then, the pulse injected to the ring shrinks its width by TLSB when it propagates through a single PSB. Suppose that the pulsewidth becomes almost equal to Toffset but still slightly wider than that after the pulse signal propagates (k − 1)th PSB, as shown in Fig. 7, then the pulse arrives at the next PSB shortly thereafter to shrink its width below Toffset. Since the output of the PSB at the opposite side of the ring is supposed to have a signal transition of an opposite polarity when the propagating pulsewidth Tpw becomes equal to the original built-in offset pulsewidth Toffset, the kth PSB output rises later than the falling edge of the (N + k)th PSB output, thus the kth DFF alters its output from 0 to 1, as illustrated in Fig. 8. By identifying this DFF output transition, this TDC detects the original built-in Toffset and triggers the completion signal. Therefore, even if Toffset fluctuates due to process variation, the absolute value of Toffset has no impact on the conversion process. Since Toffset is chosen by design to satisfy Toffset > Tth in Fig. 3, the proposed TDC does not suffer from the nonuniform shrinking rate issue.
The number of pulse rotation in the ring R is counted by the counter connected to (2N − 1)th PSB, whereas the other counter connected to (N − 1)th PSB is used to fix a false count caused by the delay of the completion detection circuit.
- Low power and high density.
- Low area, power and delay.
- Less hardware complicity.