Proposed Title :
Two-step TDC implementation using pulse-shrinking fine stage with built in coarse gain calibration using GDI based NAND gate
Improvement of this Project:
To implement fine TDC based on Pulse Shrinking Buffer Ring (PSBR) using Gate Diffusion Input(GDI) method.
To implement A 16-bit 2.0-ps Resolution Two-Step TDC adder in 45nm and 180nm using CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration
- TANNER EDA
In recent design of CMOS technology will increases efficiency in all domain, such as signal processing, image processing, digital arithmetic applications and so on. Here in this paper presents a CMOS implementation with signal processing method of time to digital converter, it will focus on wide range in two step and fine resolution of pulse shrinking method with compared to existing pulse shrinking method. Here this TS ( two-step) TDC ( Time to digital converter) will present in 16-bit rage of 2.0ps resolution and given a supply voltage to 1.8V. Finally this method will developed in 45nm and 180nm of CMOS technology with built in coarse gain calibration. This proposed architecture of PSBR ( Pulse shrinking buffer ring) will designed using GDI (Gate Diffusion input) method to reduce the MOSFET’S, area and power. This method will compared and proved in all the terms of area, delay and power.
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A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage
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