Proposed Title :
FPGA Implementation of Ternary Reversible and Non-Reversible Carry Look ahead adder design
Improvement of this Project:
To design Reversible Ternary logic full adder circuits and Non-Reversible Ternary logic full adder circuits using cascaded method of Ternary Reversible and Non Reversible Half adder.
To design a 8-bit Non-Reversible carry look ahead adder, and 8-bit Reversible carry look ahead adder and compare all the parameters.
In this paper presents a simplified summation of circuit implementation is greater that the equivalent binary logic representation, which leads to more compact circuit realization, it’s one of the key reason for the use of ternary logic systems. This is particularly appealing for quantum computation method and minimizing their number in one of the primary goals during synthesis. As a result, a ternary reversible logic synthesis has inspired, its deals with fundamental unit of information called quarts that can exist in one of the three states 0, 1 and 2. In this paper presents a reversible and non-reversible logic function of half adder, full adder and carry lookahead adder with using this ternary logic method. Finally this work implemented in verilog HDL and synthesized in Xilinx FPGA, and compared all the parameters in terms of area, delay and power.
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A Review on Fundamentals of Ternary Reversible Logic Circuits
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