Proposed Title :

FPGA Implementation of 8-Bit Parallel LMS Adaptive Beamforming Architecture using Two 4-Bit Stages

Improvement of this project :

• To design a 8-Input DRC-pLMS Beam former Architecture using two 4-Bit Linear Combiner with two 4-Bit Weight Update.

• To increases the Bit size and number of filter order in parallel LMS structure, and increases the efficiency.
  

Software Implementation:

• Modelsim
• Xilinx

Proposed System:

In this research, we offer a pipelined hardware implementation of a reduced complexity parallel least mean square (RC-pLMS) for adaptive beamforming. The overall error signal is obtained as a composite of individual stage of defects  in RC-pLMS, which is constituted by two least mean square (LMS) stage massively parallel (pLMS). The pLMS has been further condensed by removing the second independent set of weights, and its providing in a pLMS (RC-pLMS) architecture with less complexity. This proposed used with the delay and sum relaxation approach to get a pipelined hardware architecture for our proposed RC-pLMS algorithm (DRC-pLMS). The recommended design delivers a maximum operating frequency and its take maximum resource utilizations, according to synthesize and implementation results. The proposed effort of this work to re-modified the DRC-pLMS architecture with two 4-bit input levels instead to increases the efficiency. Finally this work was developed into Verilog HDL, and synthesized in Xilinx Vertex-5 FPGA and compared all the parameters in terms of area, delay and power.

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A Pipelined Reduced Complexity Two Stages Parallel LMS Structure for Adaptive Beam forming