Source : VHDL

Abstract:
The need of low area and high speed Multiplier  is  increasing  as  the  need  of  high  speed processors  are  needed.  The multipliers used in Square and cube architecture have to be more efficient in area and also in speed. In this paper a multiplier is implemented based on Nikhilam sutra with binary excess unit. The ripple carry adder in the multiplier architecture increases the speed of addition of partial products. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.

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