Proposed Title :

A 45 nm CMOS Implementation of Low Power and High Speed Voltage Level Shifter

Improvement of this Project:

• To design the proposed level shifter and current mirror level shifter and differential cascade voltage level shifter at 45 nm and 180 nm CMOS Technology and proved the performance of area, delay and power.

Software implementation:

• Tanner EDA

Proposed System:

The efficient and very low power voltage level shifter is briefly discussed in the paper, the switching speed is increased day by day in analog and digital signal processing applications while the dynamic power consumption also decreased by adopting a new regulated cross coupled method of pull up network. The proposed level shifter may transform input signal with voltage levels far lower than a MOS device threshold voltage to greater nominal supply voltage levels.  Even though to low number of components, the proposed level shifter method occupies a tiny silicon area with ultra low power consumptions by making it appropriate low power applications such as implanted medical devices and wireless sensor networks. the results of this work analyzed in Tanner EDA tool at 180 nm and 45 nm CMOS technology. The power dissipation and propagation delay of the proposed level shifter are 1.173 mW respectively, for low / high supply voltage of 0.4/1.8V and input frequency of 1 MHz .

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A Low Power and High Speed Voltage Level Shifter Based on a Regulated Cross Coupled Pull Up Network