Proposed Title :

CMOS Implementation of Inter leaving Stacked 14-T SRAM method of 5 x 32 Static – Dynamic Decoder Integration on 22 nm and 16 nm technology

Improvement of this Project:

• To design a Radiation Hardened 14-Transistor SRAM Bit Cell in the method of ILS-14T SRAM cell and Stacked 14-T SRAM cell using 22nm and 16nm CMOS Technology and proved the comparisons.

• To design a Decoder 5×32 with 32-bit SRAM Integration in two method of ILS and Stacked.

Software implementation:

• Tanner EDA

Proposed System:

In a recent technology of Static random access memory is susceptible to the high energy particles under harsh radiation environments with more storage area and creating soft error rate in SRAM cell, and it’s creating sensitivity with latching single event transient (SET) and single event upset (SEU), thus it’s taken more power consumptions and more noise margin. Therefore the proposed work of Radiation hardened of 14T SRAM cell will get solution to resolve this problem in low power consumption with low read noise margin at 0.3 to 0.9 voltage with speed and power optimization. Additionally, this proposed work where design this static – dynamic decoder integration with inter leaving stacked 14-T SRAM at 32-bit in 22nm and 16nm CMOS technology with using 0.3 V ~ 0.9 input voltage. Finally this work where designed in Tanner EDA, and proved the comparison in terms of MOSFET’s, Area and power.

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Radiation-Hardened 0.3–0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications

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