Proposed Title :

FPGA Implementation of High Throughput Encoder and Decoder design of Lossless Canonical Huffman Machine

Improvement of this project :

• To Develop this design of High Throughput Hardware design of Canonical Huffman Machine will take 160 Data Bits and compressed data bits is 90 Data Bits with compared all the parameters in terms of area, delay and power.
• To Develop the design of High Throughput design of Canonical Huffman Decoder will take 90 Data Bits as an input and decompressed into 160 Data Bits original data, and compared all the parameters in terms of area, delay and power.

Software Implementation:

• Modelsim
• Xilinx

Proposed System:

In a recent technology of digital network will transfer and receive the data with more complexity due to number of data bits and number of memory operations, thus it will take more data losses and low throughputs. Therefore, this proposed work of this paper present lossless data compression with less memory architecture using Canonical Huffman compression technique. In this case here, Huffman machine will present lossless and less memory configuration and its support multi bit operations on data compression. Here, this technique will present input as 640 Data Bits and compressed output as 90 Data bits using variable length with Canonical Huffman encoding method, and same will be decompressor 90 Data bits to 640 Data Bits using Canonical Huffman decoding method. Finally, this work will present in Verilog HDL and synthesized in Vertex FPGA and get the results of area, delay and power.

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Reconfigurable Architecture for Real-time Decoding of Canonical Huffman Codes