A 65-nm CMOS Constant Current Source With Reduced PVT Variation

Description

Existing System:

The current reference is of paramount importance because it is one of the most essential building blocks in analog or mixed-signal systems. For instance, it is used to bias operational amplifiers (op-amps), oscillators, phase-locked loops, and data converters. To support reliable operation of such circuits and systems, the current reference must have good temperature stability over a wide temperature operating range as well as high tolerance against process variations. Besides, under potential large fluctuationsof supply voltage, it is necessary for the current reference to provide good line sensitivity. Various current reference designs have been reported in. These works are generally classified into three categories. They are theVTH-based current reference, the summing current reference using a proportional-toabsolute-temperature (PTAT) current and a complementaryto-absolute-temperature current, and the voltage-to-current (VI) convertor using a compensation voltage across a resistor. Among the three techniques, the VTH-based current references are implemented using a tracking self-biasing topology or a separately biasing topology. The key advantage is that of the reduction of process dependence. This is mainly due to the process tracking property of a VTH-based voltage driving transistor, which allows it to bias a similar type of counterpart that defines the current generation. Therefore, the process-tolerant VTH-based design will be one of the focuses of this paper. Oguey and Aebischer presented a self-biased topology by means of biasing a triode-biased nMOS transistor through a saturation-biased transistor in a circuit feedback loop for current generation. However, it has difficulty canceling the temperature effect arising from the matching between the mobility temperature exponent and the mobility degradation factor. Besides, the VTH mismatch issue between the tracking device pair will degrade the current accuracy. Due to the topology, the current reference suffers from poor line sensitivity (10%/V). All of these nonideal effects cause the accuracy of the reference current to deviate significantly from the process variations (∼±30%). Alternatively, a low-voltage, low-power MOSFET-only self-biased current source was reported in.

As the technology is further scaled down to sub100 nm, the performance of current references will be degraded by the process–voltage–temperature (PVT) variations. This stems from the fact that the process variations arising from the lithography imperfections and uncontrollable factors such as random dopant fluctuations, the well proximity effect, and layout-dependent stress variation impose challenges for robust circuit designs. In addition, the MOS transistors suffer from a high current leakage level. The temperature-fluctuation-induced variation in the carrier mobility becomes significantly higher for MOSFET devices in the exemplary 65-nm CMOS technology than in the 0.18-μm technology. Finally, the short-channel effect (SCE) contributes another factor that limits the circuit performance in advanced nanometer technology. In brief, the lower the channel length in a technology, the more difficult it is to achieve a stable reference design because of the relatively poor output characteristic of long channel transistors compared with those with higher channel lengths in technologies. As a consequence, the design in a 65-nm process turns out to be more challenging than that in other processes (>65 nm) even when transistors with larger than the minimum size are used. Therefore, these problems have increased the motivation for the design of a low-power constant current reference with reduced PVT variation in the context of aggressively scaled nanometer technology. The outcome of the new design will lead to simple trimming or no trimming, depending on the specifications and applications.

Disadvantages:

• High Power Consumption
• High area coverage

Proposed System:

The constant current generation is devised from a process-tolerant temperature-compensated VI converter. It aims at establishing a constantVTH0reference compensation voltage having a first-order T.C. with reduced process sensitivity in series with another auxiliary compensation voltage having a second-order T.C. with low process sensitivity. Thecombined temperature characteristic will match the corresponding linear T.C. and nonlinear T.C. of the integrated resistor in the VIconverter. The outcome leads to a constant current reference with reduced PVT variation. The operation principle of this proposed circuit is illustrated in Fig. 1.

A process-tolerant bias current (IPTol) and a processtracking voltage (VPTrack) are generated through the IPTol and VPTrack bias circuits in self-biasing topology. When a scaledIPTol is injected into a MOSFET transistor, it will generate a gate–source voltage VGS(T) with a firstorder negative T.C., as shown in Fig. 1(a). Fig. 1(c) depicts the target reference compensation voltage VR_Comp(T) that is formed by summing the nonlinear auxiliary compensation voltage VAux_Comp(T) in Fig. 1(b) with the gate–source voltage VGS(T). On the other hand, VAux_Comp(T) is synthesized from the current-to-voltage (IV)conversionin which the scaledIPTol is passed to an active resistor. The resistor realization is based on a scaled VPTrack to bias the gate of the triode transistor. Since VR_Comp(T) exhibits a similar T.C. to the sense resistor RO(T)with the temperature characteristic shown in Fig. 1(d), the final output currentIREF can be made temperature independent over the operating temperature range as illustrated in Fig. 1(e)

Advantages:

• Reduced Power Consumption
• Reduced Area coverage