Proposed Title :

Multiple Precision Floating Point Multiplier Implementation on FPGA employing segmented and innovative architecture of DO RCA, CSA 4:2 Compressor, Parallel Full Adder (PFA), and Parallel Half Adder (PHA)

Improvement of this project :

• Improved the performance of Multi Precision floating point multiplier at 16-bit, 32-bit and 64-bit size with using segmented multiplication.

• The novelty architecture of Multi Precision module design using DO RCA, CSA 4:2 Compressor, Parallel Full Adder (PFA) and Parallel Half Adder (PHA).

Future idea for Enhancement :

• Only three precision modes (“00” -> 16 bit (Half Precision), “01” -> 32 bit (Single Precision), “10” -> 64 bit (Double Precision), and “11” -> —NA—) were created in this study. At 128 bits, the “11” combination is the next level of work, and 128 floating point multiplication is known as Quadruple Precision.

• For area and power reductions, this study employed an estimated multiplier, however Precision Multiplier was mentioned. Similarly, the segmented multiplier will only provide approximate output, thus in future work, we must create this architecture with an exact multiplier.

Software implementation:

• Modelsim
• Xilinx

Proposed System:

There is a growing need for applications in high-performance computing and artificial intelligence (AI) that require programmable accelerators with varying degrees of accuracy. Because of this, the floating-point processing element, which is the most fundamental component of the accelerators, is required in order to fulfill multiple-precision requirements while maintaining an efficient use of energy. However, the proposed structures that use high-precision-split and low-precision-combination approaches both result in a lengthy multitier processing duration and a low usage rate of the multiplication array. A programmable floating point multiple-precision processing element architecture utilizing the low-precision-combination structure is presented as a potential solution in this article. There is support for a half precision, a single precision, and a double precision method. Its utilizing segmented multiplication, regarding help to improve the functionality of the Multi Precision floating point multiplier in 16-bit, 32-bit, and 64-bit sizes respectively. The innovative architecture of the Multi Precision module design, which makes use of a Double output (DO)-RCA, CSA 4:2 Compressor, Parallel Full Adder (PFA), and Parallel Half Adder (PHA). In the end, this work was built in Verilog HDL, validated with Modelsim, synthesized with Xilinx Vertex-5 FPGA, and all of the characteristics were compared with regard to area, delay, and power.

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A Configurable Floating Point Multiple Precision Processing Element for HPC and AI Converged Computing