Proposed Title :
FPGA Implementation of Data Encoding and Decoding Technique for Energy Consumption in NOC
In existing system, the number of transitions from 0 to 1 for two consecutive flits (the flit
that just traversed and the one which is about to traverse the link) is counted. If the number is larger than half of the link width, the inversion will be performed to reduce the number of 0 to 1 transitions when the flit is transferred via the link. This technique is only concerned about the self-switching without worrying the coupling switching. Note that the coupling capacitance in the state-of–the-art silicon technology is considerably larger (e.g., four times) compared with the self-capacitance, and hence, should be considered in any scheme proposed for the link power reduction.
The scheme dealt with reducing the coupling switching. In this method, a complex encoder counts the number of Type I (Table I) transitions with a weighting coefficient of one and the number of Type II transitions with the weighting coefficient of two. If the number is larger than half of the link width, the inversion will be performed. In addition to the complex encoder, the technique only works on the patterns whose full inversion leads to the link power reduction while not considering the patterns whose full inversions may lead to higher link power consumption. Therefore, the link power reduction achieved through this technique is not as large as it could be. This scheme was also based on the hop-by-hop technique. A coding technique is reduces the coupling switching activity by taking the advantage of end-to-end encoding. It is based on lowering the coupling switching activity by eliminating only Type II transitions.
- Switching activity is high
In the proposed system we are additionally design the decoder for scheme 3 and reduce the switching activity of the decoder.
In this input flit is given in W-1 bit with one bit for indication for encoded or not. If the bit is 1 then data is encoded else no encoding is take place for the data.
The internal block diagram of block D of decoder circuit changes according to each scheme. In decoders the inverse operation of encoder takes place. There is need of only one block Ty to determine which action has to be taken.
In the proposed encoding scheme II, we make use of both odd (as discussed previously) and full inversion. The full inversion operation converts Type II transitions to Type IV transitions. The scheme compares the current data with the previous one to decide whether the odd, full, or no inversion of the current data can give rise to the link power reduction.
In the encoding Scheme III, even inversion to Scheme II is added. The reason is that odd inversion converts some of Type I transitions to Type II transitions. As can be observed from Table II, if the flit is even inverted, the transitions indicated as in the table are converted to Type IV/ Type III transitions. Therefore, the even inversion may reduce the link power dissipation as well. The scheme compares the current data with the previous one to decide whether odd, even, full, or no inversion of the current data can give rise to the link power reduction.
- Switching activity is low
- Model sim
- Xilinx 14.2
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