Proposed Title :
An Efficient Approach of Highly Reliable RHBD 10T Memory Cell For Aerospace Applications
Improvement of this Project:
Implementation of RHBD 10T memory cell using 45nm CMOS Technology and compared in terms of area, power.
- TANNER EDA
SRAMs have been widely adopted in various aerospace electronic systems, and play a major role in the delay, area, power, and critical reliability. In aerospace applications, SRAMs have a key constrain that makes a challenge in the reliability induced by energetic particles. Therefore, single event upsets (SEUs) are a major reliability failure mechanism that can cause a malfunctioning of an electronic system by altering the stored value temporarily. When the charged particle hits a sensitive node of an integrated circuit, the induced charge along its path can be efficiently collected and accumulated through drift processes. Once a transient voltage pulse generated by the accumulated charge is above the switching threshold of the circuit, the stored value in this sensitive node will be changed. However, it is the fact that the SRAM cell (i.e., 6T) is usually built using two cross-coupled inverters, and the changed value in a stored node can also trigger the positive feedback mechanism to flip the state in another sensitive node so that an error occurs in the memory. Because these corrupted data can be fully recovered by overwriting operations, such a phenomenon is also reported as the soft error.
Generally, with CMOS process technology scaling, SRAM cells are more vulnerable to this reliability challenge because of increasing densities, decreasing critical charge, and reducing supply voltage. Hence, soft error robustness with radiation-hardened by-design (RHBD) techniques is an increasingly important prerequisite in aerospace applications due to the above reasons and more complex cosmic radiation environment, and proposing a novel area-efficient and high-reliability RHBD memory cell is needed.
Recently, several remarkable RHBD cell studies have been reported based on circuit-level redundancy or redesigning a memory cell for providing radiation fault-tolerate capability. For example, Jung et al. has presented two RHBD memory cells (PS-10Tand NS-10T memory cells) by using a stacked structure. However, due to the defect of design, these memory cells can provide only partial SEU robustness, i.e., NS-10T cell can only recover0→1 SEU instead of 1→0 SEU. In contrast, PS-10T cell has the capability of tolerating 1 →0SEU, and for 0→1 SEU, it is in capable of action. Jahinuzzaman et al have proposed an RHBDQuatro-10T memory cell to reduce only 1→0 SEU by relying on a negative feedback. In, an RHBD 11T memory cell is reported, which remains the stored value by blocking the feedback path to prevent the induced transient pulse affecting the next nodes. However, for this RHBD 11T memory cell, due to the single-ended structure, the differential write and read capabilities are not enabled, which can increase its operation time. In, a DICE memory cell is proposed using 12 transistors, which makes use of two interlocked latch pairs to store the complementary values so that an affected value can be recovered to its original value using the positive feedback. Redesigning a cell structure and using a shallow trench isolation technique, an RHBD 12T memory cell is proposed at the cost of large area overhead. However, the common drawback of 11T, DICE, and 12T cells is that their area overheads are larger. Hence, all of the above RHBD cells are not suitable for aerospace applications in which RHBD memory cells with both area-efficient and higher liability properties are required in order to offer appropriate design for-reliability systems.
- Increasing densities
- Decreasing Critical Charges
- Reducing Supply Voltages
Schematic and Normal Operation Analysis
For the proposed RHBD 10T memory cell, Fig. 1 describes its basic schematic structure. From this figure, it can be seen that the proposed RHBD memory cell consists of ten transistors in which PMOS transistors are transistors P1∼P6, and the remaining transistors (N1∼N4) are NMOS transistors. Both NMOS transistorsN4 and N3 are defined as the access transistors, and their gates are connected with a word line (WL). Hence, when this WL is in high mode (WL=1), two access transistors are turned ON. At the moment, write/read operation can be implemented. The stored nodes are nodes Q, QN, S1, and S0 in which these four nodes are responsible for keeping the stored value correctly. In order to quickly transmit the digital signal to the output port during a read operation, a differential sense amplifier has to be employed and connected with two bit lines BL and BLN.
Assuming that the stored value of the proposed RHBD 10Tmemory cell is 1 in digital logic, i.e., Q=1, QN=0, S1=1, and S0 =0, as shown in Fig. 1. It is easily concluded that the proposed RHBD 10T memory cell is steadily maintaining the stored value when WL is driven by a low voltage (WL=0). Before normal read operation, due to pre charge circuitry, the voltages of the bit lines BL and BLN will be raised to 1 in digital logic. In read operation, WL is in high mode (WL=1), and then two access transistorsN3 and N4 are turned ON immediately. Nodes Q, QN, S1, andS0 are keeping the stored value, and the voltage of bit line BL is also unchanged. However, the voltage of bit line BLN is decreased due to the discharge operation through ON transistors N1 and N3.Once the voltage difference of bit lines is a constant value which has been confirmed in the differential sense amplifier connecting with two bit lines, the stored digital signal in memory cell will be output as soon as possible. The purpose of write operation is to change the stored logical value correctly. Therefore, before write operation, due to the write circuitry, the voltages of bit line BL will be 0 in digital logic. Contrary to the voltage of bit line BL, the voltage of bit line BLN will be 1. When the voltage of WL is supply voltage VDD(WL =1), write operation is executed. Transistors N2, P2, P3, andP6 are turned ON. At the moment, the states of transistors N1, P1,P4, and P5 will be OFF, so that the logical value of this memory cell is rightly changed to 0. Therefore, write operation can also be completed successfully.
- More Complex Cosmic radiation environment
- Novel Area efficient
- High Reliability RHBD Memory Cell
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Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications
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