Proposed Title :

• ER-TCAM: A Ternary Based Soft Error Resilient SRAM Content Addressable FPGA Memory

Improvement of this Project:

• Enhanced ER-TCAM Size up to 2048 x 40, and proved with existing ER-TCAM Size 64×40, 512×40, 1024×40.

Software implementation:

• Modelsim
• Xilinx 14.2

Proposed Abstract:

In a Software defined networking (SDN) in packet classification and open flow applications which using static random access (SRAM) based ternary content addressable memory (TCAM) on field programmable gate arrays (FPGAs). Thus, SRAM based TCAMs will using major part in all FPGA based applications, it will support to reduced vulnerable to soft errors with high search performance and reduced critical path delay. In brief SRAM based TCAM will reduce the cost and reduce the response time with single bit parity fault detection, which also covered minimal critical path overhead. This technique exploits the binary encoded TCAM table maintained SRAM based TCAM for updated purpose to implement a low response time error correction. The proposed work of this paper will present SRAM based TCAM using error detection with error correction with different TCAM sizes 64×40, 512×40, 1024×40, 2048×40. Finally this work was designed in Verilog HDL, Synthesized in Xilinx Vertex 5 FPGA and proved the performance of area, delay and power.

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ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs

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