Proposed Title :
FPGA Implementation of Adaptive Edge
Directed Interpolation Algorithm using Carry Skip Adder
Improvement of this project :
To design Adaptive Edge Directed Interpolation Algorithm with using Carry Skip Adder to reduced delay and power consumptions.
Using 256×256 image resolutions, to prove the performance of PSNR
Developed and integrated all the hardware machine with RCA and CSKA. Synthesized this work in Xilinx Spartan 6 FPGA and
proved the performance of area, delay and power.
Software Implementation:
- Modelsim
- Xilinx
Proposed System:
The term “demosaicking” refers to the process of recreating a full-color image using only the partial color samples that were obtained by a single-chip image sensor. Therefore, interpolation is required in order to acquire the missing color pixels. An adaptive edge-directed interpolation method that employs an edge estimator for the interpolation has been proposed in this study, along with a hardware architecture for the algorithm’s implementation. We may be able to improve the image’s resolution on both sides if we give green the highest priority throughout the color interpolation process and make use of a strategy that involves pooling hardware resources. In order to accommodate the hardware sharing strategy for red, green, and blue interpolation, arithmetic operations will need more logic sizes, and the VLSI design will require a higher gate count. A color demosaicking approach that makes use of a carry skip adder as opposed to a normal ripple carry adder would be included into all existing ways for hardware sharing as part of the project. This would allow for a reduction in the amount of area, time, and energy that would be required. Experiments are carried out as part of this study making use of the VHDL programming language and the synthesis capabilities of the Xilinx FPGA XC6SLX150-2CSG484 at a clock frequency of 200 MHz in order to develop a color demosaicking method using 256 by 256 pixel pictures.
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Hardware Architecture for Adaptive Edge Directed Interpolation Algorithm
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