Proposed Title :

FPGA Implementation Adiabatic Quantum Flux Parametron technique based 16-Bit BCD adder using Majority Gate

Improvement of this Project:

• • • To implement RCA based BCD adder and CLA based BCD adder using AQFP (Adiabatic Quantum Plux Parametron) majority gate.

    • • To implement this in 16-bit size of RCA_BCD adder and CFA_BCD adder and shown the parameter value of area, delay and power.

Software implementation:

• Modelsim
• Xilinx 14.2

 Proposed System:

In this recent digital design of BCD (Binary Coded Decimal) adders, which have lot of functionality in digital arithmetic applications, in such as this BCD adder will have lot of complexity in variable bit size and also intermediate carry operations. In existing method of BCD adder will added a Correction logic in between two 4-bit Binary adder, to correct a intermediate Carry operation, with using Majority gate functionality. In this paper we present to reduced the complexity of this BCD adder design which using Adiabatic Qunatum Flux Parametron technique in Majority gate, thus the correction logic operation will improve the performance of area, delay and power, and also reduced the complexity in BCD adders. Here, we are present this BCD adder using RCA (Ripple Carry Adder) and CFA (Carry Flow Adder) methods, in this CFA 1-bit adder will also have Majority gates, thus it will give more performance compared to RCA. Finally this paper presents in VHDL language and Synthesized in Xilinx FPGA S6LX9-2TQ144, and also compared in the terms of area, delay and power.

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