A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS
In recent years, there has been a significant interest in the design of ultralow-voltage (ULV) and ultralow-power (ULP) analog circuits, dedicated for applications powered from nonconventional energy sources (energy harvesters). In order to meet the requirements posed by such sources, a number of innovative circuit solutions have recently been developed, operating from supply voltages (VDD) as low as 0.25–0.3 V. The most interesting solutions include unbuffered op-amps linear transconductors and delta–sigma modulators (DSMs). In most cases, the authors exploit the concept of subthreshold biased bulk-driven (BD) transistors that allow overcoming issues of poor signal swing when the supply voltage is comparable or even less than the threshold voltage (VTH) of the employed MOS transistors. It is also worth to point out that most often the authors exploit different versions of 0.13-μm technology with relatively low |VTH|, approximately equal to 0.25 V.
One of the greatest challenges for analog designers dealing with sub-0.5-V circuits is the realization of power efficient and precise analog-to-digital converters (ADCs). Among different architectures, the ADCs based on clock-less asynchronous DSMs (ADSMs) have gained considerable attention in recent years, because of their potential advantages for applications in ULP wireless sensor nodes. The ADSM translates a band-limited analog input signal to an asynchronous duty-cycle modulated square wave, which can then be digitized with a time-to-digital converter. Owing to its principle of operation, the circuit has a simple structure, does not require any clocking, is free of quantization noise, has good frequency response, and offers good accuracy at very low supply voltages. It is also worth to point out that ADSM architecture is well compatible with contemporary CMOS technologies. An interesting approach to the design of an ULV ADSM based on BD building blocks and exploiting a single-ended RC integrator has recently been proposed. The circuit offers reasonable performance in an ULV environment, nevertheless, it was realized using low VTH CMOS process and required several off-chip passive elements. In this paper, a new approach to the design of an ULV ADSM is presented. The proposed circuit offers similar performance as the one described but can operate with much lower relative supply voltage (VDD/VTH). The fully differential architecture of this circuit allows reducing the even harmonics of the output signal, thus improving the linearity and consequently the resolution of ADSM. In addition, since the RC integrator has been replaced with a Gm–C integrator in the proposed design, the above-mentioned external RC elements applied are avoided, which is another advantage of the proposed solution. The design experimentally confirms proper operation of the transconductor and the common-mode feedback (CMFB) circuit, which in original papers was validated only by simulations. In addition, a new ULV BD comparator has been designed and investigated. All the blocks were designed and optimized for application in ULV ADSM and the design tradeoffs for such application have been discussed. The design experimentally confirms the feasibility of the proposed circuits and investigates their performance in ULV ADSM.
- More Quantization noise occur
- More complicated circuit with required multiple of clock signals
- Higher relative supply voltage
- More Harmonics in Output signals
In recent years, ULV – (ultra low voltage) BD (bulk driven) circuits are significant in wireless applications powered form non-conventional energy sources. ADC and DAC are surviving an important role in analog and digital circuits. A Delta-Sigma Modulator (DSM) method used for encoding in data convertor technique. In existing, with 1-bit DAC, a fully differential ADSM designed. In this proposed system, which proven the minimum supply voltage of 0.25V for ADSN (Asynchronous Delta Sigma Modulator) is designed with eight-bit cell DAC. A proposed ADSM designed with DAC 8 bit cell, with the help of Gm-C integrator and hysteretic comparator. Finally, the proposed circuit is implemented in the TANNER EDA at 45nm CMOS Technology with 0.25V input voltage and proved the comparison in terms of area and power.
- Principle of Operation
- Second order Effects
TRANSISTOR LEVEL REALIZATION:
In the proposed design, the Gm–C approach has been used to design a voltage integrator. The Gm–C integrators provide better power efficiency and larger input resistance than their RC counterparts and allow avoiding large resistors which are difficult to integrate. The Gm–C integrator employed in the considered design [Fig. 2(a)] consists of the BD linear transconductor and the CMFB circuit. The Gm stage is characterized by excellent linearity of its transfer characteristic, even for VDD as low as 0.25 V. Assuming operation in the subthreshold region and neglecting the impact of the finite output resistances of MOS transistors, the HD3 nonlinear distortion, determined for the transconductor with outputs shorted to mid supply (VCM), is given as
The CMFB circuit exploited in the considered design [Fig. 2(b)] is characterized by large insensitivity to differential signals, without employing a resistive voltage divider at its input. The first feature allows minimizing the nonlinear distortion introduced by this circuit, while the second one ensures its input resistance to be sufficiently large for the considered application. The quiescent values of |VDS| voltages at all internal nodes of the integrator have been chosen slightly above VDD/2 (5–10 mV). This ensures the maximum voltage headroom that allows the circuit to accommodate for possible process and temperature variations, namely, avoiding the operation of all transistors in the triode region. The same principle has been applied in other blocks of the ADSM.
The hysteretic comparator (Fig. 3) has been implemented as a BD open-loop amplifier loaded with a negative resistance load (NRL). Its input differential amplifier (M15–M17) is based on the solution first described. Despite the lack of the tail current source, which is a very desirable feature in sub-0.5-V design, the circuit behaves as a truly differential amplifier with sufficiently high common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR). In addition, due to the transconductance boosting circuitry (M16A,B), its dc voltage gain is improved by 6 dB as compared with a common BD differential pair. The built-in hysteresis is realized in a standard way with the NRL circuit composed of transistors M22–M23.
The hysteresis threshold (H) depends on the ratio of the aspect ratios of the diode-connected transistors M22 and the cross-coupled transistors M23. It should be noted here that according to (11), the smaller the hysteresis, the lower the nonlinear distortion of the ADSM. Therefore, the hysteresis threshold should be as small as possible. Its minimum size is limited by transistor mismatches. The simulated hysteresis threshold in this project was 3.12 mV. Its standard deviation was 0.85 mV (results of the Monte Carlo mismatch analysis, 100 runs). The set of the current mirrors (M18–M22) is used to realize the differential output of the comparator. The additional inverters (Inv1 and Inv2) are used to further improve the quality of the output waveform.
The 1-bit DAC exploited in the considered design is shown in Fig. 4. The circuit consists of four current sources/sinks, realized with transistors M24C,D, M25B,C, and four switches M26A,B and M27A,B. The input terminals (gates) of the switches are controlled with the output signals of the ADSM. Depending on the output voltage levels, the DAC outputs sink or source a current equal to IB (5 nA). Thus, the 1-bit DAC can be considered as a fully differential switched-current source. The mismatched currents (ID24C, ID24D, ID25B, and ID25C) for the 1-bit DAC add up to the mismatched currents ID6A, ID6B, ID8A, and ID8B of the input transconductor, thus increasing the input offset of the ADSM (VOS), and consequently affecting the duty cycle of the generated waveform for Vin = 0, which is given as
- Less Quantization noise
- Less complicated circuit with no required clock signals
- Lower relative supply voltage
- Less Harmonics in Output signals
- Its improving linearity and consequently the resolution of ADSM
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A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS
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