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vedic divider

Low Power Divider Using Vedic Mathematics

Original price was: ₹16,000.00.Current price is: ₹10,000.00.

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Source Code : VHDL

Abstract:

Vedic mathematics is a unique technique of carrying out mathematical computations and it has its roots in the ancient Indian Mathematics. This paper presents the divider architecture using one of the Vedic mathematics techniques called as Paravartya-Yojayet, which means to transpose and apply. This paper proposes a fast, low power and cost effective architecture of a divider using the ancient Indian Vedic division algorithm. The merits of the proposed architecture are proved by comparing the gate count, power consumption and delay against the conventional divider architectures. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.

List of the following  materials will be included with the Downloaded Backup:

1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Existing and Proposed Project Comparison
3. Architecture Diagram
4. Algorithm with Flow chart
5. Report for Phase1 and Phase2
6. Proposed abstract document
7. Reference materials
8. Literature survey with Reference Document
9. Online Support ( Team viewer/ Ammy Admin)

Proposed System:

  • Increases Bit size of  4:8 to 8:16 bits

Advantages:

  • Reduced the Power
  • Reduced area and efficiency

Software used:                                                           

  • Modelsim
  • Xilinx

 

 

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vedic divider Low Power Divider Using Vedic...

Original price was: ₹16,000.00.Current price is: ₹10,000.00.

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