Proposed Title :

FPGA Implementation of Energy Efficient ECG Signal Processing based on Approximate Pruned Haar Discrete Wavelet Transform

Improvement of this project :

• To design a Approximate Haar Wavelet Transform of Hardware architecture at three level of design ( Original HDWT, Approximate HDWT, Approximate Pruned HDWT ) using Conventional Full adder and XOR-MUX Full adder to reduced the number of logic size and power consumptions.

Software Implementation:

• Modelsim
• Xilinx 

Proposed System:

The methodology of approximation computing emerged as an ideal approach that allowed for the transfer of accuracy and energy efficiency. Error-tolerant programmes, which include signal processing and multimedia processing, are able to process the information with an accuracy that is lower than the norm while still satisfying a high and appropriate service quality at the application level. The important phase that comes just before the processing and analysis of an electrocardiogram (ECG) data is the automated recognition of R-peaks within the ECG signal. The Haar discrete wavelet transform (HDWT) is a low-complexity pre-processing filter that is appropriate for detecting ECG R-peaks in embedded systems such as wearable devices, which are subject to very stringent energy constraints. In this study, an approximate HDWT hardware architecture for ECG processing is presented with MIT-BIH Database. The energy efficiency of this design is quite good. Only 7 improvements are necessary for our top suggestion, which involves doing pruning inside the basic concept of the HDWT hardware design. The use of a truncation technique to improve energy efficiency is also investigated in this article by observing the development of the signal-to-noise ratio and the ultimate impact in the ECG peak-detection application. The proposed approach of this work gather about the effectiveness of the technique based on HDWT approximation hardware design approach using XOR MUX Full adder design instead of Conventional Full Adder design, and also design with higher levels of truncation than the normal HDWT. When we combined our HDWT matrix approximation proposal with the pruning and the highest acceptable level of truncation, our results showed a reduction in energy consumption that was approximately nine times greater than the previous level. Finally this work developed in Verilog HDL, and Synthesized on Xilinx Vertex-5 FPGA and compared all the parameters in terms of area, delay and power.

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Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing